MT8941B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT8941B Datasheet PDF : 27 Pages
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MT8941B
Data Sheet
When MS2 is HIGH, the F0b pin provides the frame pulse output compatible with the ST-BUS format and locked to
the internal or external input signal as determined by the other mode select pins.
Table 4 summarizes the modes of the two DPLL. It should be noted that each of the major modes selected for DPLL
#2 can have any of the minor modes, although some of the combinations are functionally similar. The required
operation of both DPLL #1 and DPLL #2 must be considered when determining MS0-MS3.
Mode F0b
C4b
C8Kb
CVb
#
(kHz) (MHz) (kHz) (MHz)
0
i:8
i:4.096
i:X
o:1.544
1
i:X
o:4.096
i:8
o:1.544
2
o:8
i:4.096
i:X
o:1.544
3
o:8
o:4.096
i:8
o:1.544
4
i:8
i:4.096
i:X
i:1.544
5
i:X
o:4.096
o:8
i:1.544
6
o:8
i:4.096
i:X
i:1.544
7
o:8
o:4.096
o:8
i:1.544
8
i:8
i:4.096
i:X
o:1.544
9
i:16
o:4.096
i:X
o:1.544
10
o:8
i:4.096
i:X
o:1.544
11
o:8
o:4.096
i:X
o:1.544
12
i:8
i:4.096
i:X
i:2.408
13
i:X
o:4.096
o:8
i:2.408
14
o:8
i:4.096
i:X
i:2.408
15
o:8
o:4.096
o:8
i:2.408
Note: i: Input
o: Output
X: “don’t care” input. Connect to VDD or VSS.
Table 5 - Functions of the Bidirectional Signals in Each Mode
The direction and frequency of each of the bidirectional signals are listed in Table 5 for each of the given modes in
Table 4.
Jitter Performance and Lock-in Range
The output jitter of a DPLL is composed of the intrinsic jitter, measured when no jitter is present at the input, and the
output jitter resulting from jitter on the input signal. The spectrum of the intrinsic jitter for both DPLLs of the
MT8941B is shown in Figure 5. The typical peak-to-peak value for this jitter is 0.07UI. The transfer function, which
is the ratio of the output jitter to the input jitter (both measured at a particular frequency), is shown in Figure 6 for
DPLL #1 and Figure 7 for DPLL #2. The transfer function is measured when the peak-to-peak amplitude of the
sinusoidal input jitter conforms to the following:
10 Hz - 100 Hz : 13.6 µs
100 Hz - 10 kHz : 20 dB/decade roll-off
> 10 kHz
: 97.2 ns
The ability of a DPLL to phase-lock the input signal to the reference signal and to remain locked depends upon its
lock-in range. The lock-in range of the DPLL is specified in terms of the maximum frequency variation in the 8 kHz
reference signal. It is also directly affected by the oscillator frequency tolerance. Table 6 lists different values for the
lock-in range and the corresponding oscillator frequency tolerance for DPLL #1 and DPLL #2. The smaller the
tolerance value, the larger the lock-in range.
9
Zarlink Semiconductor Inc.
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