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MT8941B

Advanced T1/CEPT Digital Trunk PLL

Zarlink Semiconductor Inc 

MT8941B

Data Sheet

Input-to-Output Phase Relationship

The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possible for the relative phase of

the reference signal to swing inside the no-correction window depending on its jitter and the relative drift of the

master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in

case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum

phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32 µs. However, this phase difference can be absorbed

by the input jitter buffer of Zarlink’s T1/CEPT devices.

The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the

reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter

buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame.

The circuit will remain in synchronization as long as the input frequency is within the lock-in range of the DPLLs

(refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough

to meet the CCITT line rate specification (1.544 MHz ±32 ppm and 2.048 MHz ±50 ppm) for the High Capacity

Terrestrial Digital Service.

The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1,

which locks to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions

are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized to the falling edge of the input

signal (8 kHz). The master clock source is specified to be 12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2

over the entire temperature range of operation.

The inputs MS0 to MS3 are used to select the operating mode of the MT8941B, see Tables 1 to 4. All the outputs

are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is

available for use in applications involving Zarlink’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790

(CEPT Interfaces).

Modes of Operation

The operation of the MT8941B is categorized into major modes and minor modes. The major modes are defined for

both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are

applicable only to DPLL #2. There are no minor modes for DPLL #1.

Major modes of DPLL #1

DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in

NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse

F0i (8 kHz). DPLL #1 requires a master clock input of 12.352 MHz (C12i). In the second and third major modes

(MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The

division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is

connected internally to DPLL #2, which operates in SINGLE CLOCK mode.

Major modes of DPLL #2

There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes

DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals.

In NORMAL mode, DPLL #2 provides the CEPT/ST-BUS compatible timing signals locked to the falling edge of the

8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and

the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE-

RUN mode if the C8Kb pin is tied to VDD or VSS.

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Zarlink Semiconductor Inc.

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