73M2910L 데이터 시트보기 (PDF) - TDK Corporation
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73M2910L Datasheet PDF : 35 Pages
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73M2910L
Microcontroller
After a reset, the USR1 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure a low current state at reset
(you don’t want to drive out against external inputs, and you don’t want floating inputs).
USR2 PORT
USR2 Port Data SFR Address 0D8H
Bit Addressable
Reset State 00h
BIT 7
USR2.7
BIT 6
USR2.6
BIT 5
USR2.5
BIT 4
USR2.4
BIT 3
USR2.3
BIT 2
USR2.2
BIT 1
USR2.1
BIT 0
USR2.0
Bits in this register will be asserted on the USR2(7:0) pins if the corresponding direction register bit is a 0.
Reading this SFR’s address will return data reflecting the values of pins USR2(7:0) except when address 0D8h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.
USR2 Port Direction (DIR2) SFR Address 0D9H
Byte Addressable
Reset State FFh
BIT 7
DIR2.7
BIT 6
DIR2.6
BIT 5
DIR2.5
BIT 4
DIR2.4
BIT 3
DIR2.3
BIT 2
DIR2.2
BIT 1
DIR2.1
BIT 0
DIR2.0
This register is used to designate the USR2 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR2 pin is programmed as an output that will be driven by the corresponding USR2 I/O data
register bit. If the register bit is a 1, the corresponding pin will treated as an input.
After a reset, the USR2 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure a low current state at reset (you don’t want to
drive out against external inputs, and you don’t want floating inputs).
USR3 PORT
USR3 Port Data External address 0000h
Byte Addressable
Reset State 00h
BIT 7
USR3.7
BIT 6
USR3.6
BIT 5
USR3.5
BIT 4
USR3.4
BIT 3
USR3.3
BIT 2
USR3.2
BIT 1
USR3.1
BIT 0
USR3.0
Bits in this register will be asserted on the USR3(7:0) pins if the corresponding direction register bit is a 0.
Reading this SFR’s address will return data reflecting the values of pins USR3(7:0).
If the bank select feature is chosen, the USR3.7 pin acts as address bit 17 and USR3 data bit 7 is ignored.
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