73M2910L 데이터 시트보기 (PDF) - TDK Corporation

부품명

상세내역

일치하는 목록

73M2910L

Microcontroller

TDK Corporation 

73M2910L

Microcontroller

DESCRIPTION (continued)

The 73M2910L has two extra interrupt sources, an

external interrupt and a HDLC interrupt. The HDLC

interrupt has two registers associated with it; the

HDLC Interrupt Register which is used to determine

the source of the interrupt, and the HDLC Interrupt

Enable Register that enables the source of the

interrupt.

The state of the external interrupts can be read

through a register allowing the interrupt pins to be

used as inputs. The interrupt pins INT0 and INT1

can be either negative edge, positive edge or level

triggered. The INT2 pin is always edge triggered.

Two buffered clock outputs have been added to

support peripheral functions such as UARTs,

modems and other clocked devices. The main

internal processor clock frequency can be divided by

2 for power conservation in functional modes that

only require half the clock speed.

Additional internal special function registers are

used for firmware control over the HDLC Packetizer,

the clocks and the programmable I/O ports.

To accommodate processor peripherals when

operating at higher frequencies, the processor’s

timing has been altered to allow more address setup

time for slower peripheral program ROM and

memory mapped peripherals.

For low power applications the 73M2910L supports

two power conservation modes: idle and power-down.

In the power-down state the total current consumption

is less than 10 µA at room temperature.

DEVELOPER’S NOTE:

The 73M2910L is also available in a

100-Pin PGA package for system developers. The

PGA package is more convenient and reliable for

development emulation systems than the other

package styles. Emulation systems for the

73M2910L are available through Signum Systems,

11992 Challenger Court, Moorpark, CA 93021

(805) 523-9774.

8032 REFERENCE

This Document will describe the features unique to

the 73M2910L. Please refer to a 8032 Programmer’s

Guide, Architectural Overview and Hardware

Description for details on the instruction set, timers,

UART, interrupt control, and memory structure.

2

Share Link: