73M2910L 데이터 시트보기 (PDF) - TDK Corporation

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73M2910L

Microcontroller

TDK Corporation 

73M2910L

Microcontroller

INTERRUPTS (continued)

EXTERNAL INTERRUPT DIRECTION REGISTER (IDIR) SFR ADDRESS 092h

Byte Addressable

Reset State 00h

BIT 7

0

BIT 6

0

BIT 5

INT@

BIT 4

INT!

BIT 3

INT)

BIT 2

INTD2

BIT 1

INTD1

BIT 0

INTD0

These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt

and will also allow the user to directly read the logic level at the pads INT(2:0).

BITS (5:3) INT(2:0)

Bits (5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected by

bits (2:0).

BITS (2:0) Interrupt Polarity Control

If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1, a rising edge will trigger the

interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high

and the internal pin signal to the timer controls will be inverted.

Bits 6 and 7 will always be read as 0’s.

CLOCK CONTROL REGISTER SFR ADDRESS 0DAh

Byte Addressable

Reset State 00h

BIT 7

Activity

BIT 6

CLK1

CTRL1

BIT 5

MCLK

CTRL

BIT 4

CLK2EN

BIT 3

CLK2

CTRL1

BIT 2

CLK2

CTRL0

BIT 1

CLK1EN

BIT 0

CLK1

CTRL0

These bits determine the behavior at the CLK1OUT and CLK2OUT pins and allow the user to divide the main

internal processor clock frequency by two for power conservation.

BIT 7

Bit 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the

73M2910L from entering sleep mode.

BIT 6

When bit 6 = 1, CLK1OUT will be OSC/1.5 if bit 1 is a 1 and bit 0 is 0.

BIT 5

0

1

CLOCK OUT

OSC

OSC/2

BIT 5 Master Clock Control

When bit 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, the

processor clock is the same frequency as the oscillator’s.

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