73M2910L 데이터 시트보기 (PDF) - TDK Corporation
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73M2910L Datasheet PDF : 35 Pages
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73M2910L
Microcontroller
The chip selects partition a 64K memory space as follows:
CHIP SELECT PIN
RESERVED FOR INTERNAL USE
CS0 (USR4.0)
CS1 (USR4.1)
CS2 (USR4.2)
CS3 (USR4.3)
CS4 (USR4.4)
CS5 (USR4.5)
CS6 (USR4.6)
CS7 (USR4.7)
ADDRESS
0000H - 00FFH
0100H - 01FFH
0200H - 03FFH
0400H - 07FFH
0800H - 0FFFH
1000H - 1FFFH
2000H - 3FFFH
4000H - 7FFFH
8000H - FFFFH
# BYTES
256
256
512
1K
2K
4K
8K
16K
32K
NOTE:External addresses 0000H-00FFH may not be read. These are reserved for 73M2910L internally defined
registers
USR5 PORT
USR5 Port Register External Address 0006h
Byte Addressable
Reset State 60h
BIT 7
USR5EN
BIT 6
USR5.0
BIT 5
USR5.1
BIT 4
POL5.0
BIT 3
POL5.1
BIT 2
ACTE0
BIT 1
ACTE1
BIT 0
AND01
This register allows user programmable wakeup capability. If this is not required, this register can be used to
read external signals at the USR5.1 and USR5.0 pins.
Bit 7 USR5 Input Port Enable
Bit 7 is used to enable the USR5.1 and USR5.0 input circuitry. If this bit is a 0, the USR5 pin output circuitry is
driven to a known level internally and any signal level at the pin is ignored. When set to a 1 the pin input
circuitry is enabled and the values of these pins are reflected in bits 6 and 7. If these pins are not connected at
the board level, this bit should remain at a 0 to keep the pin input circuitry from drawing unnecessary current.
The USR5 Register can be programmed such that a transition (bit 4 determines rising or falling) of USR5.0, a
transition (bit 3 determines rising or falling) of USR5.1, or the logical combination of USR5.0 (bit 4 determines
high or low level) AND USR5.1 (bit 3 determines high or low level) can wakeup the processor from its
power-down mode.
BIT 6 USR5.0
Bit 6 reflects the value of chip pin USR5.0 if the USR5EN bit is set to a 1.
BIT 5 USR5.1
Bit 5 reflects the value of chip pin USR5.1 if the USR5EN bit is set to a 1.
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