MT8940 데이터 시트보기 (PDF) - Mitel Networks
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MT8940 Datasheet PDF : 16 Pages
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ISO-CMOS MT8940
Pin Description (continued)
Pin #
10
11
12
13
14
15
16
17
18,19
20
21
22
23
24
Name
C8Kb
C4o
VSS
C4b
C2o
C2o
ENC2o
MS3
Ai, Bi
Yo
CVb
CV
RST
VDD
Description
Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100K
internal resistor to VDD) - This is the 8 kHz input signal on the rising edge of which DPLL #2
locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs
an 8 kHz signal provided by DPLL #1, which is also connected internally to DPLL #2.
Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
Ground (0 Volt)
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input (pulled
internally to VDD) to an external clock at 4.096 MHz.
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by ENC2o (pin 16).
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by ENC2o (pin 16).
Enable 2.048 MHz clock (TTL compatible input) - This active high input (pulled internally
to VDD) enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are
in high impedance condition.
Mode select 3 input (TTL compatible) - This input (pulled internally to VDD) in conjunction
with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.)
Inputs A and B (TTL compatible) -These are the two inputs (pulled internally to VSS) of the
uncommitted NAND gate.
Output Y (Totem pole output) - Output of the uncommitted NAND gate.
Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input (pulled internally to VDD) to an external clock at 1.544 MHz or 2.048 MHz to provide the
internal signal at 8 kHz to DPLL #2.
Variable clock (Three state output) - This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled ENCV (pin 1).
Reset (Schmitt trigger input) -This input (active LOW) evokes reset condition for the
device.
VDD (+5V) Power supply.
3-29
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