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MT8940

ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL

Mitel Networks 

MT8940 ISO-CMOS

ENVC 1

MS0 2

C12i 3

MS1 4

F0i 5

F0b 6

MS2 7

C16i 8

ENC4o 9

C8Kb 10

C4o 11

VSS 12

24 VDD

23 RST

22 CV

21 CVb

20 Yo

19 Bi

18 Ai

17 MS3

16 ENC2o

15 C2o

14 C2o

13 C4b

Figure 2 - Pin Connections

Pin Description

Pin #

1

2

3

4

5

6

7

8

9

Name

ENCV

MS0

C12i

MS1

F0i

F0b

MS2

C16i

ENC4o

Description

Variable clock enable (TTL compatible input) - This input (pulled internally to VDD) directly

controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables

CV and when LOW, puts it in high impedance condition. It also controls the three states of

CVb signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when

LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.

Mode select ‘0’ input (TTL compatible) - This input (pulled internally to VSS) in conjunction

with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and

2).

Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz ±100ppm

for DPLL #1.

Mode select-1 input (TTL compatible) - This input (pulled internally to VSS) in conjunction

with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and

2)

Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to

VDD) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544

MHz) clock.

Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending

on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts

as an input (pulled internally to VDD) to an external frame pulse.

Mode select-2 input (TTL compatible) - This input (pulled internally to VDD) in conjunction

with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)

Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz±32 ppm for

DPLL #2.

Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally

to VDD) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance

condition.

3-28

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