MT8940 데이터 시트보기 (PDF) - Mitel Networks
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MT8940 Datasheet PDF : 16 Pages
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ISO-CMOS MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 9)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
tF15H
-40
75 ns
2
CVb output (1.544 MHz) rise
time
tr1.5
10 15 ns Test load circuit 1 (Fig. 17).
3
CVb output (1.544 MHz) fall
D time
P
4 L CVb output (1.544 MHz) clock
L period
tf1.5
12 15
tP15 648
690
5
CVb output (1.544 MHz) clock
#1 width (HIGH)
tW15H 320
386
ns Test load circuit 1 (Fig. 17).
ns
ns
6
CVb output (1.544 MHz) clock
width (LOW)
tW15L 314
327 ns
7
CV delay (HIGH to LOW)
t15HL
5 30 ns
8
CV delay (LOW to HIGH)
t15LH
-12 10 ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
F0i
VIH
VIL
tF15H
tW15H
tP15
tf1.5
CVb
VOH
VOL
t15HL
t15LH
tW15L
tr1.5
CV
VOH
VOL
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 10)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1
C8Kb output (8kHz) delay
(HIGH to HIGH)
tC8HH
130 ns Test load circuit 2 (Fig. 17).
2
D
P
C8Kb output (8 kHz) delay
(LOW to LOW)
3 L C8Kb output duty cycle
L
tC8LL
50 130 ns Test load circuit 2 (Fig. 17).
66
% In Divide -1 Mode
50
% In Divide - 2 Mode
4
#1
Inverted clock output delay
(HIGH to LOW)
tICHL
40 75 ns
5
Inverted clock output delay
(LOW to HIGH)
tICLH
35 60 ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-37
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