TC58NVG0S3AFT05 데이터 시트보기 (PDF) - Toshiba

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TC58NVG0S3AFT05

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

TC58NVG0S3AFT05

(11) When five address cycles are input

Although the device may read in a fifth address, it is ignored inside the chip.

Read operation

CLE

CE

WE

ALE

I/O

00h

RY / BY

Program operation

Address input

30h

Ignored

Figure 22.

CLE

CE

WE

ALE

I/O

80h

Address input

Ignored

Figure 23.

Data input

2003-08-20A 28/33

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