MT8941B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT8941B

Advanced T1/CEPT Digital Trunk PLL

Zarlink Semiconductor Inc 

MT8941B

Data Sheet

Crystal Clock

(16.384 MHz)

MT8941B

DPLL #1 - NOT USED

DPLL #2 - FREE-RUN MODE

(MS0=1; MS1=0;MS2=1;

MS3=1)

MT8941B

MS0

VDD

MS1

MS2

C4o

MS3

F0i

C12i

C4b

ENCV

C8Kb

C2o

C16i

ENC4o

ENC2o

C2o

Ai

Bi

F0b

VSS RST

C

R

ST-BUS

TIMING

SIGNALS

Crystal Clock

(16.384 MHz)

DPLL #1 - NOT USED

DPLL #2 - NORMAL MODE

(MS0=0; MS1=0;

MS2=1; MS3=1)

VDD

MS0

VDD

MS1

MS2

C4o

MS3

F0i

C12i

C4b

ENCV

C8Kb

C2o

C16i

ENC4o

ENC2o

C2o

Ai

Bi

F0b

VSS RST

C

R

Figure 13 - Generation of the ST-BUS Timing Signals

ST-BUS

TIMING

SIGNALS

VDD

Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.

Parameter

Symbol

Min.

Max.

1 Supply Voltage

VDD

-0.3

7.0

2 Voltage on any pin

VI

VSS-0.3

VDD+0.3

3 Input/Output Diode Current

IIK/OK

±10

4 Output Source or Sink Current

IO

±25

5 DC Supply or Ground Current

IDD/ISS

±50

6 Storage Temperature

TST

-55

125

7 Package Power Dissipation - Plastic DIP

PD

- PLCC

PD

1200

600

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Units

V

V

mA

mA

mA

oC

mW

mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics

Sym. Min. Typ.‡ Max. Units

Test Conditions

1 Supply Voltage

VDD

4.5

5.0

5.5

V

2 Input HIGH Voltage

VIH

2.0

VDD

V

3 Input LOW Voltage

VIL

VSS

0.8

V

4 Operating Temperature

TA

-40

25

85

oC

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

17

Zarlink Semiconductor Inc.

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