MT8941B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT8941B

Advanced T1/CEPT Digital Trunk PLL

Zarlink Semiconductor Inc 

MT8941B

Data Sheet

Crystal Clock

(16.384 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i

C12i

ENCV

C8Kb

C16i

ENC4o

ENC2o

VDD

C4b

C2o

F0b

Yo

VSS RST

MH89790B

DSTi

C2i

DSTo

F0i

CSTi0

CSTi1

CSTo

OUTA

OUTB

TRANSMIT

RxT

RECEIVE

RxR

MT8980/81

ST-BUS

SWITCH

CEPT

PRIMARY

MULTIPLEX

DIGITAL

LINK

VDD

Mode of Operation for the MT8941B

C

R

DPLL #1 - NOT USED

DPLL #2 - FREE-RUN (MS0=1; MS1=0; MS2=1; MS3=1)

Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link

At the slave end of the link (Figure 10) both the DPLLs are in NORMAL mode, with DPLL #2 providing the ST-BUS

timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The

regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock, which is the same as the master

end.

The 12.352 MHz and 16.384 MHz crystal clock sources are necessary for DPLL #1 and #2, respectively.

Synchronization and Timing Signals for the CEPT Transmission Link

The MT8941B can be used to provide the timing and synchronization signals for the MH89790/790B, Zarlink’s

CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT

primary multiplex digital trunk are the same, only DPLL #2 is required.

15

Zarlink Semiconductor Inc.

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