MAX127ACAI(2012) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX127ACAI
(Rev.:2012)

Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface

Maxim Integrated 

MAX127/MAX128

Multirange, +5V, 12-Bit DAS with

2-Wire Serial Interface

SDA A2

A1

A0

SCL

SHDN

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

REF

REFADJ

ANALOG

INPUT

MUX

AND SIGNAL

CONDITIONING

2.5V

REFERENCE

10kΩ

SERIAL INTERFACE LOGIC

INT

CLOCK

T/H

AV =

1.638

OUT

IN

REF

CLOCK

12-BIT SAR ADC

MAX127

MAX128

VDD

AGND

DGND

Figure 1. Block Diagram

Detailed Description

Converter Operation

The MAX127/MAX128 multirange, fault-tolerant ADCs use

successive approximation and internal track/hold (T/H) cir-

cuitry to convert an analog signal to a 12-bit digital output.

Figure 1 shows the block diagram for these devices.

Analog-Input Track/Hold

The T/H circuitry enters its tracking/acquisition mode on

the falling edge of the sixth clock in the 8-bit input control

word and enters its hold/conversion mode when the mas-

ter issues a STOP condition. For timing information, see

the Start a Conversion section.

Input Range and Protection

The MAX127/MAX128 have software-selectable input

ranges. Each analog input channel can be independently

programmed to one of four ranges by setting the appro-

priate control bits (RNG, BIP) in the control byte (Table

1). The MAX127 has selectable input ranges extending

to ±10V (±VREF x 2.441), while the MAX128 has select-

able input ranges extending to ±VREF. Note that when an

external reference is applied at REFADJ, the voltage at

REF is given by VREF = 1.638 x VREFADJ (2.4 < VREF <

4.18). Figure 2 shows the equivalent input circuit.

A resistor network on each analog input provides a

±16.5V fault protection for all channels. This circuit limits

the current going into or out of the pin to less than 1.2mA,

whether or not the channel is on. This provides an added

layer of protection when momentary overvoltages occur at

the selected input channel, and when a negative signal is

R1

CH_

BIPOLAR

S1

VOLTAGE

REFERENCE

5.12kΩ

S2

R2

UNIPOLAR

OFF

CHOLD

ON

S3

TRACK

HOLD

TRACK

S4

T/H

OUT

HOLD

S1 = BIPOLAR/UNIPOLAR SWITCH

S2 = INPUT MUX SWITCH

S3, S4 = T/H SWITCH

R1 = 12.5kΩ (MAX127) OR 5.12kΩ (MAX128)

R2 = 8.67kΩ (MAX127) OR ∞ (MAX128)

Figure 2. Equivalent Input Circuit

applied at the input even though the device may be con-

figured for unipolar mode. Overvoltage protection is active

even if the device is in power-down mode or VDD = 0V.

Digital Interface

The MAX127/MAX128 feature a 2-wire serial interface

consisting of the SDA and SCL pins. SDA is the data I/O

and SCL is the serial clock input, controlled by the master

device. A2–A0 are used to program the MAX127/MAX128

to different slave addresses. (The MAX127/MAX128

only work as slaves.) The two bus lines (SDA and SCL)

must be high when the bus is not in use. External pullup

resistors (1kΩ or greater) are required on SDA and SCL

to maintain I2C compatibility. Table 1 shows the input

control-byte format.

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