MAX127ACAI(2012) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX127ACAI Datasheet PDF : 16 Pages
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MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7μF at REF; external clock, fCLK = 400kHz;
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
DIGITAL INPUTS (SDA, SCL)
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (SDA)
Output Low Voltage
Three-State Output Capacitance
SYMBOL
CONDITIONS
VIH
VIL
VHYS
IIN
CIN
VIN = 0V or VDD
(Note 4)
VOL
COUT
ISINK = 3mA
ISINK = 6mA
(Note 4)
MIN TYP MAX UNITS
0.7 x VDD V
0.3 x VDD
V
0.05 x VDD
V
±0.1 ±10
µA
15
pF
0.4
V
0.6
15
pF
Timing Characteristics
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7μF at REF pin; TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
2-WIRE FAST MODE
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Transmitting)
Set-Up Time for STOP Condition
Capacitive Load for Each
Bus Line
Pulse Width of Spike Suppressed
SYMBOL
CONDITIONS
fSCL
tBUF
tHD,STA
tLOW
tHIGH
tSU,STA
tHD,DAT
tSU,DAT
tR
Cb = Total capacitance of one bus line in pF
tF
Cb = Total capacitance of one bus line in pF
tF
Cb = Total capacitance of one bus line in pF
tSU,STO
Cb
tSP
MIN TYP
1.3
0.6
1.3
0.6
0.6
0
100
20 +
0.1 x Cb
20 +
0.1 x Cb
20 +
0.1 x Cb
0.6
0
MAX UNITS
400
kHz
µs
µs
µs
µs
µs
0.9
µs
ns
300
ns
300
ns
250
ns
µs
400
pF
50
ns
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