MAX127ACAI(2012) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX127ACAI Datasheet PDF : 16 Pages
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MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Timing Characteristics (continued)
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7μF at REF pin; TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
2-WIRE STANDARD MODE
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Transmitting)
Setup Time for STOP Condition
Capacitive Load for Each
Bus Line
Pulse Width of Spike Suppressed
SYMBOL
CONDITIONS
fSCL
tBUF
tHD,STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
tF
tF
tSU, STO
Cb = total capacitance of one bus line in pF,
up to 6mA sink
Cb
tSP
MIN TYP
4.7
4.0
4.7
4.0
4.7
0
250
20 +
0.1 x Cb
4.0
0
MAX UNITS
100
kHz
µs
µs
µs
µs
µs
0.9
µs
ns
1000
ns
300
ns
250
ns
µs
400
pF
50
ns
Note 1: Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-Supply
Rejection test.
Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel, sine wave applied to all “off” channels.
Note 4: Guaranteed by design. Not tested.
Note 5: Use static external load during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Note 8: Not subject to production testing. Provided for design guidance only.
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