MAX127ACAI(2012) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX127ACAI
(Rev.:2012)

Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface

Maxim Integrated 

MAX127/MAX128

Multirange, +5V, 12-Bit DAS with

2-Wire Serial Interface

Pin Description

PIN

NARROW PDIP

SSOP

1, 2

1, 2

3, 9, 22, 24

4, 7, 8, 11, 22,

24, 25, 28

4

3

5

5

6, 8, 10

6, 10, 12

7

9

11

12

13–20

21

13

14

15–21, 23

26

23

27

NAME

FUNCTION

VDD

N.C.

+5V Supply. Bypass with a 0.1μF capacitor to AGND.

No Connection. No internal connection.

DGND

SCL

A0, A2, A1

SDA

SHDN

AGND

CH0–CH7

REFADJ

REF

Digital Ground

Serial Clock Input

Address Select Inputs

Open-Drain Serial Data I/O. Input data is clocked in on the rising edge of

SCL, and output data is clocked out on the falling edge of SCL.

External pullup resistor required.

Shutdown Input. When low, device is in full power-down (FULLPD) mode.

Connect high for normal operation.

Analog Ground

Analog Input Channels

Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with

a 0.01µF capacitor to AGND. Connect to VDD when using an external

reference at REF.

Reference Buffer Output/ADC Reference Input. In internal reference mode,

the reference buffer provides a 4.096V nominal output, externally adjustable

at REFADJ. In external reference mode, disable the internal reference by

pulling REFADJ to VDD and applying the external reference to REF.

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