IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CSB LOW
W/RB
MBB
ENB
LOW
tENS2
tENS2
tENH
tENH
tCLK
tCLKH tCLKL
COMMERCIAL TEMPERATURE RANGE
FFB
B0-B35
CLKA
HIGH
tDS
tDH
W1
(1)
tSKEW1
tCLK
tCLKH tCLKL
1
EFA FIFO2 Empty
2
tREF
tREF
CSA
W/RA
LOW
LOW
MBA LOW
ENA
tENS2
tENH
A0-A35
tA
W1
4660 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
20