IDT72V3622L10PFG 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V3622L10PFG

3.3 VOLT CMOS SyncBiFIFO™ 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

tCLKH

tCLK

tCLKL

CSB LOW

W/RB LOW

MBB

tENS2

tENS2

tENH

tENH

ENB

IRB HIGH

tDS

tDH

B0 - B35

CLKA

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

2

ORA FIFO2 Empty

CSA LOW

W/RA LOW

MBA LOW

ENA

A0- A35

Old Data in FIFO2 Output Register

3

tREF

tREF

tENS2

tA

tENH

W1

4660 drw 12

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.

If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA

cycle later than shown.

Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)

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