IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA
tCLKH
tCLK
tCLKL
COMMERCIAL TEMPERATURE RANGE
FFA/IRA HIGH
CSA
W/RA
MBA
ENA
A0 - A35
NOTE:
1. Written to FIFO1.
tENS1
tENS2
tENH
tENH
tENS2
tENH
tENS2
tENH
tDS
tDH
W1(1)
tENS2
tENH
tENS2
tENH
W2 (1)
No Operation
4660 drw 06
Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKB
tCLKH
tCLK
tCLKL
FFB/IRB HIGH
CSB
W/RB
MBB
ENB
B0 - B35
tENS1
tENS2
tENH
tENH
tENS2
tENS2
tENH
tENH
tDS
tDH
W1(1)
tENS2
tENH
W2(1)
tENS2
tENH
No Operation
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
15
4660 drw 07