IDT72V3622L10PFG 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V3622L10PFG

3.3 VOLT CMOS SyncBiFIFO™ 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKB

tCLK

tCLKH

tCLKL

CSB LOW

W/RB HIGH

MBB LOW

ENB

tENS2

tENH

COMMERCIAL TEMPERATURE RANGE

ORB

B0- B35

HIGH

tA

Previous Word in FIFO1 Output Register

tSKEW1(1)

CLKA

IRA FIFO1 Full

CSA LOW

tCLK

tCLKH

tCLKL

1

Next Word From FIFO1

2

tWEF

tWEF

W/RA HIGH

MBA

ENA

A0 - A35

tENS2

tENS2

tENH

tENH

tDS

tDH

Write

To FIFO1

4660 drw 14

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)

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