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IDT72511

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

IDT’s BiFIFO family is versatile for both multiprocessor

and peripheral applications. Data can be sent through both

FIFO memories concurrently, thus freeing both processors

from laborious direct memory access (DMA) protocols and

frequent interrupts.

Two full 18-bit wide FIFOs are integrated into the IDT

BiFIFO, making simultaneous data exchange possible. Each

FIFO is monitored by separate internal read and write point-

ers, so communication is not only bidirectional, it is also

totally independent in each direction. The processor con-

nected to Port A of the BiFIFO can send or receive mes-

sages directly to the Port B device using the BiFIFO’s 9-bit

bypass path.

The BiFIFO can be used in different bus configurations:

18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be

used for the 18- to 18-bit configuration, and two BiFIFOs are

required for 36- to 36-bit configuration. This configuration

can be extended to wider bus widths (54- to 54-bits, 72- to

72-bits, …) by adding more BiFIFOs to the configuration.

The microprocessor or microcontroller connected to Port

A controls all operations of the BiFIFO. Thus, all Port A

interface pins are inputs driven by the controlling processor.

Port B can be programmed to interface either with a second

processor or a peripheral device. When Port B is programmed

in processor interface mode, the Port B interface pins are

inputs driven by the second processor. If a peripheral device

is connected to the BiFIFO, Port B is programmed to periph-

eral interface mode and the interface pins are outputs.

18- to 18-bit Configurations

A single BiFIFO can be configured to connect an 18-bit

processor to another 18-bit processor or an 18-bit peripheral.

The upper BiFIFO shown in each of the Figures 1 and 2 can

be used in 18- to 18-bit configurations for processor and

peripheral interface modes respectively.

36- to 36-bit Configurations

In a 36- to 36-bit configuration, two BiFIFOs operate in

parallel. Both BiFIFOs are programmed simultaneously, 18

data bits to each device. Figures 1 and 2 show multiple

BiFIFOs configured for processor and peripheral interface

modes respectively.

Processor Interface Mode

When a microprocessor or microcontroller is connected to

Port B, all BiFIFOs in the configuration must be programmed

to processor interface mode. In this mode, all Port B inter-

face controls are inputs. Both REQ and CLK pins should be

pulled LOW to ensure that the setup and hold time require-

ments for these pins are met during reset. Figure 1 shows

the BiFIFO in processor interface mode.

Processor

A

Address

Control

IDT

BiFIFO

Cntl A

Cntl B

ACK

REQ

CLK

Data A Data B

Processor

B

Control

Data

36

IDT

BiFIFO

Data

36

RAM

Cntl A

Cntl B

ACK

REQ

CLK

Data A Data B

18

18

RAM

2668 drw 05

Figure 1. 36-Bit Processor to 36-Bit Processor Configuration

NOTE:

1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA,

and DSA; Cntl B refers to R/WB and DSB or RB and WB.

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