IDT72511 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

일치하는 목록

IDT72511

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

CONFIGURATION REGISTER 5 FORMAT

Bit

Function

0

Select Port B Interface

0

RB and WB or DSB and R/WB

1

1

Unused

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Pins are RB and WB (Intel-style interface)

Pins are DSB and R/WB (Motorola-style interface)

2

Full Flag Definition

0 Write pointer meets read pointer

1 Write pointer meets reread pointer

3

Empty Flag Definition

0 Read pointer meets write pointer

1 Read pointer meets rewrite pointer

4

REQ Pin Polarity

0 REQ pin active HIGH

1 REQ pin active LOW

5

ACK Pin Polarity

0 ACK pin active LOW

1 ACK pin active HIGH

7-6 REQ / ACK Timing

00 2 internal clocks between REQ assertion and ACK assertion

01 3 internal clocks between REQ assertion and ACK assertion

10 4 internal clocks between REQ assertion and ACK assertion

8

Port B Read & Write

Timing Control for Peripheral Mode

11 5 internal clocks between REQ assertion and ACK assertion

0 RB, WB, and DSB are asserted for 1 internal clock

1 RB, WB, and DSB are asserted for 2 internal clocks

9

Internal Clock

Frequency Control

0 Internal clock = CLK

1 Internal clock = CLK divided by 2

10

Port B Interface

Mode Control

0 Processor interface mode (Port B controls are inputs)

1 Peripheral interface mode (Port B controls are outputs)

11

Unused

12

Unused

13

Unused

14

Unused

15

Unused

Table 10. BiFIFO Configuration Register 5 Format

2668 tbl 12

CONFIGURATION REGISTER 6 FORMAT

15

6

5

4

3

2

Unused

PIO5

PIO4

PIO3

PIO2

Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data

1

PIO1

0

PIO0

2668 tbl 13

CONFIGURATION REGISTER 7 FORMAT

15

Unused

6

5

MIO5

4

MIO4

3

MIO3

2

MIO2

1

MIO1

Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask

0

MIO0

2668 tbl 14

5.32

11

Share Link: