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IDT72511

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

DA0-DA17

CSA

DSA

R/WA

A0, A1

DB0-DB17

RB (DSB)

WB (R/WB)

RER

REW

LDRER

LDREW

REQ

ACK

CLK

FLGA-

FLGD

PIO0-PIO5

RS

VCC

GND

Name

I/O

Description

Data A

I/O Data inputs and outputs for the 18-bit Port A bus.

Chip Select A I Port A is accessed when Chip Select A is LOW.

Data Strobe

I Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is

A

read out of Port A on the falling edge of Data Strobe when Chip Select is LOW.

Read/Write A

I This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH,

data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data

is written into Port A on the rising edge of DSA.

Addresses

I When Chip Select A is asserted, A 0, A1, and Read/Write A are used to select one of six internal

resources.

Data B

I/O Data inputs and outputs for the 18-bit Port B bus.

Read B

Write B

I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is

programmed to peripheral mode this pin functions as an output. This pin can function as part of

an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style

interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is

read on the falling edge of DSB or written on the rising edge of DSB through Port B. The default

is Intel-style processor mode. (RB as an input).

I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is

programmed to peripheral mode this pin functions as an output. This pin can function as part of

an Intel-style interface (WB) or as part of a Motorola-style interface (R/ WB). As an Intel-style

interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is

read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B

falling or rising edge. The default is Intel-style processor mode ( WB as an input.)

Reread

I Loads A→ B FIFO Read Pointer with the value of the Reread Pointer when LOW.

Rewrite

I Loads B→ A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.

Load Reread I Loads the Reread Pointer with the value of the A→B FIFO Read Pointer when HIGH.

Load Rewrite I Loads the Rewrite Pointer with the value of the B→A FIFO Write Pointer when HIGH.

Request

I When Port B is programmed in peripheral mode, asserting this pin begins a data transfer.

Request can be programmed either active HIGH or active LOW.

Acknowledge

Clock

O When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a

Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed

either active HIGH or active LOW.

I This pin is used to generate timing for ACK, RB , WB, DSB and R/WB when Port B is in the

peripheral mode.

Flags

O These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each

of the two internal FIFOs (A→B and B→A) has four internal flags: Empty, Almost-Empty,

Almost-Full and Full.

Program-

I/O Six general purpose I/O pins. The input or output direction of each pin can be set independently.

mable Inputs/

Outputs

Reset

I A LOW on this pin will perform a reset of all BiFIFO functions.

Power

There are two +5V power pins.

Ground

There are five Ground pins at 0V.

2668 tbl 01

5.32

3

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