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7641

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

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MITSUBISHI MICROCOMPUTERS

7641 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 7641 group has five timers: timer X, timer Y, timer 1, timer 2,

and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,

timer 2, and timer 3 are 8-bit timers.

All timers are down count timers. When the timer reaches “0016”

or “000016”, an underflow occurs at the next count pulse and the

corresponding timer latch is reloaded into the timer and the count

is continued. When a timer underflows, the interrupt request bit

corresponding to that timer is set to “1”.

Read and write operation on 16-bit timer must be performed for

both high and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write the

low-order byte first. The 16-bit timer cannot perform the correct

operation when reading during the write operation, or when writing

during the read operation.

SCSGCLK

Timer X internal clock

select bit

φ/8

φ / 16

φ / 32

φ / 64

Timer X count source

select bits

Timer X count

stop bit

P43/CNTR0

CNTR0 active edge

switch bit “0”

“1”

“00” “11”

“01”

Timer X

operating “10”

mode bits

Timer X (low) latch (8)

Timer X (low) (8)

Timer X write control bit

Timer X (high) latch (8)

Timer X (high) (8)

P54 direction register

CNTR0 active edge

switch bit “0”

Q

T

“1”

Q

P43 latch

Pulse output mode

Pulse width HL continuously

measurement mode

Rising edge detection

φ/8

φ / 16

φ / 32

φ / 64

P44/CNTR1

CNTR1 active

edge switch bit

“0”

Pulse output mode

Falling edge detection

Pulse width HL

continuously measurement,

Period measurement modes

Timer Y count

“00”

stop bit

“01”

Timer Y (low) latch (8) Timer Y (low) high (8)

“11”

Timer Y (low) (8)

Timer Y (high) (8)

Timer Y write

control bit

“10”

“1”

Timer Y

operating mode

bits

Timer mode,

TYOUT output enabled

Timer mode,

TYOUT output enabled

“0”

CNTR1 active

edge switch bit “1”

S

Q

T

Q

“11”

Timer Y

operating mode

bits “00”

“01”

“10”

Timer 1 count

source select bit

“0”

φ/8

f(XCIN) / 2

“1”

Timer 1 count

stop bit

Timer 1 latch (8)

Timer 1 (8)

Timers 1, 2 write control

Timers 1, 2 write control

bit

“0”

Timer 2 latch (8)

bit

Timer 2 count

source select bit “1”

Timer 2 (8)

φ

TOUT output control bit

TOUT output active “0”

edge switch bit

Q

P51/TOUT/XCOUT

TOUT source

select bit

TOUT output

control bit

T

“1”

Q

φ/8

TOUT output control bit

“0”

Q

TOUT output active “1”

edge switch bit

T

Q

“0”

Timer 3 latch (8)

“1”

Timer 3 count

source select bit

Timer 3 (8)

Fig. 19 Timer block diagram

Timer X interrupt

request

CNTR0 interrupt

request

Timer Y interrupt

request

CNTR1 interrupt

request

Timer 1 interrupt

request

Timer 2 interrupt

request

Timer 3 interrupt

request

24

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