MC33689 데이터 시트보기 (PDF) - Motorola => Freescale
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MC33689 Datasheet PDF : 18 Pages
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Freescale SMeC3m36i8c9onductor, Inc.
Prop delay symmetry: tdom max - trec
dt2
-
min
11
us
note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined in the column “condition”
LIN physical layer: bus driver timing characteristics for slow slew rate (note 1)
Dominant propagation delay Tx to LIN
tdom min
100
Dominant propagation delay Tx to LIN
tdom max
100
Recessive propagation delay Tx to LIN
trec min
100
Recessive propagation delay Tx to LIN
trec max
100
Prop delay symmetry: tdom min - trec
dt1s
-22
-
max
Prop delay symmetry: tdom max - trec
dt2s
-
23
min
us
Measurement threshold
61.6% Vsup
us
Measurement threshold
25.1% Vsup
us
Measurement threshold
38.9% Vsup
us
Measurement threshold
77.8% Vsup
us
us
note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined in the column “condition”
LIN physical layer: bus driver fast slew rate
LIN high slew rate (programming mode) Dv/Dt fast
13
V/us
Fast slew rate
LIN physical layer: receiver characteristics and wake up timings
Receiver dominant propagation delay
TrL
3.5
Receiver recessive propagation delay
TrH
3.5
Receiver prop delay symmetry
Tr-sym
-2
Bus wake up deglitcher
TpropWL
30
70
Bus wake up event reported
Twake
20
6
us
LIN low to Rx low. Note 2
6
us
LIN high to Rx high. note 2
2
us
TrL - TrH
90
us
Sleep and stop mode
us
Note 3
note 2: Measured between LIN signal threshold “Lin-vil” or “Lin-vih” and 50% of Rx signal.
note 3: Twake is typically 2 internal clock cycles after LIN rising edge detected. Ref to “LIN bus wake up behavior” figure. In sleep mode the
Vdd rise time is strongly dependant upon the decoupling capacitor at Vdd pin.
Figure 3. Test circuit for timing measurements
Vsup
Vsup
Tx
R0
LIN
Rx
C0
Gnd
R0 and C0: 1k/1nF, 660ohms/6.8nF and 500ohms/10nF
MC33689
9
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