MC33689 데이터 시트보기 (PDF) - Motorola => Freescale
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MC33689 Datasheet PDF : 18 Pages
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Freescale SMeCm33i6c89onductor, Inc.
(Vs1 and Vs2 from 5.5V to 18V and Tamb from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Min
Typ
Max
Reset pull down current
Reset Duration after Vdd High
Ipdw
1.5
8
reset-dur
0.65
1
1.35
Unit
mA
ms
IN: input
High Level Input Voltage
Vih
0.7Vdd
Vdd+0.3
V
Low Level Input Voltage
Vil
-0.3
0.3Vdd
V
Input Current
Iin
-10
10
µA
MISO: SPI output
Low Level Output Voltage
Vol
0
1.0
V
High Level Output Voltage
Voh
Vdd-0.9
Vdd
V
Tristated MISO Leakage Current
-2
+2
uA
MOSI, SCLK, CSB: SPI input
High Level Input Voltage
Vih
0.7Vdd
Vdd+0.3
Low Level Input Voltage
Vil
-0.3
0.3Vdd
V
CSB Pull up current source
Iih
-100
-20
uA
MOSI, SCK Input Current
Iin
-10
10
uA
SPI: DIGITAL INTERFACE TIMING
SPI operation frequency
Freq
0.25
4
MHz
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Falling Edge of CS to Rising
Edge of SCLK
tpCLK
250
twSCLKH
125
twSCLKL
125
tlead
100
N/A
ns
N/A
ns
N/A
ns
N/A
ns
Falling Edge of SCLK to CS Rising Edge
tlag
100
N/A
ns
MOSI to Falling Edge of SCLK
tSISU
40
N/A
ns
Falling Edge of SCLK to MOSI
tSIH
40
N/A
ns
MISO Rise Time (CL = 220pF)
trSO
25
50
ns
MISO Fall Time (CL = 220pF)
tfSO
25
50
ns
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
- MISO High Impedance
tSOEN
0
tSODIS
50
ns
50
Time from Rising Edge of SCLK to MISO
Data Valid
tvalid
0
50
ns
Conditions
Internally limited. Vdd<4V,
Vreset = 4.6V
0<VIN<Vdd
I out = 1.5mA
I out = -250uA
0V<Vmiso<Vdd
Vi 1V to 3.5V
0<VIN<Vdd
guaranteed by design
guaranteed by design
guaranteed by design
0.2 V1=<MISO>=0.8V1,
CL=100pF
guaranteed by design
MC33689
5
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