M37640E8FP 데이터 시트보기 (PDF) - Mitsumi

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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MSB D0CEN

D0CRR

D0UMIE

D0SWT

D0HRS3

D0HRS2

D0HRS1

D0HRS0

LSB

Address: 004116

Access: R/W

D0HRS3,2,1,0 DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3,2,1,0)

0000: Disable

0001: UART1 receive interrupt

0010: UART1 transmit interrupt

0011: TimerY interrupt

0100: External Interrupt 0

0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)

0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)

0111: USB EndPoint 3 IN_PKT_RDY signal (falling edge active)

1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)

1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)

1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)

1011: USB EndPoint 3 OUT_PKT_RDY signal (rising edge active)

1100: MBI OBE0 signal (rising edge active)

1101: MBI IBF0 (data) signal (rising edge active)

1110: SIO receive/transmit interrupt

1111: CNTR1 interrupt

DOSWT

DMAC Channel 0 Software Transfer Trigger (bit 4)

0: No action (Bit is always read as “0”)

1: Writing “1” requests a channel 0 transfer

D0UMIE DMAC Channel 0 USB and MBI Enable Bit (bit 5)

0: Disabled

1: Enabled

D0CRR

DMAC Channel 0 Transfer Initiation Source Capture Register Reset (bit 6)

0: No action (Bit is always read as “0”)

1: Setting to “1” causes reset of the channel 0 capture register

D0CEN

DMAC Channel 0 Enable Bit (bit 7)

0: Channel 0 disabled

1: Channel 0 enabled

Fig. 1.84. DMAC Channel 0 Mode Register 2 (DMA0M2)

MSB

7

D1CEN

D1CRR

D1UMIE

D1SWT

D1HRS3

D1HRS2

D1HRS1

D1HRS0

LSB

0

Address: 004116

Access: R/W

Reset: 0016

D1HRS3,2,1,0 DMAC Channel 1 Hardware Transfer Request Source Bits (bits 3,2,1,0)

0000: Disable

0001: UART2 receive interrupt

0010: UART2 transmit interrupt

0011: TimerX interrupt

0100: External Interrupt 1

0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)

0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)

0111: USB EndPoint 4 IN_PKT_RDY signal (falling edge active)

1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)

1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)

1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)

1011: USB EndPoint 4 OUT_PKT_RDY signal (rising edge active)

1100: MBI OBE1 signal (rising edge active)

1101: MBI IBF1 (data) signal (rising edge active)

1110: Timer interrupt

1111: CNTR0 interrupt

D1SWT

DMAC Channel 1 Software Transfer Trigger (bit 4)

0: No action (Bit is always read as “0”)

1: Writing “1” requests a channel 0 transfer

D1UMIE

DMAC Channel 1 USB and MBI Enable Bit (bit 5)

0: Disabled

1: Enabled

D1CRR

DMAC Channel 1 Transfer Initiation Source Capture Register Reset (bit 6)

0: No action (Bit is always read as “0”)

1: Setting to “1” causes reset of the channel 1 capture register

D1CEN

DMAC Channel 1 Enable Bit (bit 7)

0: Channel1 disabled

1: Channel 1 enabled

Fig. 1.85. DMAC Channel 1 Mode Register 2 (DMA1M2)

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