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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.23 DIRECT MEMORY ACCESS CONTROLLER

This device contains a two-channel Direct Memory

Access Controller (DMAC). Each channel performs

fast data transfers between any two locations in the

memory map initiated by specific peripheral events or

software triggers.

The main features of the DMAC are as follows:

• Two independent channels

• Single-byte and burst transfer modes

• 16-bit source and destination address registers

(for a 64K byte address space)

• 16-bit transfer count registers

(for up to 64K bytes transferred before underflow)

• Source/Destination register automatic

increment/decrement and no-change options

• Source/Destination/Transfer count register reload on

write or after transfer count register underflow options

• Transfer requests from USB (9), MBI (4), external

interrupts (4), UART1 (2), UART2 (2), SIO (1),

TimerX (1), TimerY (1), Timer1 (1), and

software triggers

• Closely coupled with USB and MBI for efficient data

transfers

• Interrupt generated for each channel when their

respective transfer count register underflows

• Fixed channel priority (channel 0 > channel 1)

• Two cycles of F required per byte transferred

Each channel of the DMAC is made up of the following:

• 16-bit source and destination registers

• A 16-bit transfer count register

• Two mode registers

• Status flags contained in a status register shared by

the two channels

• Control and timing logic

The 16-bit source and destination registers allow ac-

cesses to any two locations in the 64K byte memory

area. The 16-bit transfer count register decrements by

one for each transfer performed and causes an interrupt

and flag to be set when it underflows. The mode regis-

ters control the configuration and operation of the DMAC

channel associated with the registers. A block diagram

of the DMAC is shown in Figure 1.81.

The SFR addresses for the two mode, source, destina-

tion, and transfer count registers of a channel are the

same for each channel. The accessible channel regis-

ters are is determined by the value of the DMAC

Channel Index Bit (DCI) (bit 7 of the DMAC Index and

Status Register (DMAIS). When this bit is a “0”, channel

0 registers are accessible, and when this bit is a “1”,

channel 1 registers are accessible.

The configuration of DMAIS and the mode registers are

shown in Figures 1.82, 1.83, 1.84, and 1.85.

Sample timing diagrams are shown in Figures 1.86,

1.87, and 1.88, for a single-byte transfer initiated by a

hardware source, a single-byte transfer initiated by the

software trigger, and a burst transfer initiated by a hard-

ware source, respectively.

Interrupts: UART1 Rx & Tx, SIO, ExtInt0,

TimerY, CNTR1

Signals: OBE0, IBF0(data), EP1, EP2,

EP3 OUT_PKT_RDY or

IN_PKT_RDY,

EP1 OUT_FIFO_NOT_EMPTY

INT Detect, I-flag

Ch 0 Timing Generator

(D0TMS)

(D0CEN; D0CRR;

D0UMIE; D0SWT;

D0HRS3,2,1,0)

(DTSC)

Address Bus

Ch 0 Source Reg

Ch 0 Destination Reg

(D0SRCE,

D0SRID,

D0RLD)

(D0DRCE.

D0DRID,

(DRLDD) D0RLD)

(DRLDD)

Ch 0 Count Reg

Int

Gen

Interrupts: UART2 Rx & Tx, ExtInt1,

Timer1, TimerX, CNTR0

Signals: OBE1, IBF1(data), EP1, EP2,

EP4 OUT_PKT_RDY or

IN_PKT_RDY,

EP OUT_FIFO_NOT_EMPTY

INT Detect, I-flag

(D1UF, D1SFI)

Temp Reg

(D0UF,

D0SFI)

Index &

Status Reg

(D0UF)

(D0DAUE)

(D0DWC)

(D0DWC)

(D0DWC)

DMAC Ch 0

Interrupt

Mode Reg 1 Mode Reg 2

Ch 0 Source Latch

Ch 0 Destination Latch

Ch 0 Count Latch

15

0 15

0 15

0

DMAC Channel 0

Data Bus

DMAC Channel 1

Data Bus

Fig. 1.81. DMAC Block Diagram

68

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