M37640E8FP 데이터 시트보기 (PDF) - Mitsumi
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M37640E8FP Datasheet PDF : 96 Pages
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Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.22 MASTER CPU BUS INTERFACE
This device has a bus interface function with 2 I/O buff-
ers that can be operated in slave mode by control
signals from the master CPU (see Figure 1.75). Bus
Interface Circuit). The bus interface can be connected
directly to either a R/W type of CPU or a CPU with RD
and WR separate signals. Slave mode is selected
with the bit 7 of the data buffer control register 0. The
single data bus buffer mode and the double data bus
buffer mode are selected with bit 7 of the Data Bus
Buffer Control register 1. When selecting the double
data bus buffer mode, Port P72 becomes S1 input.
Prior to enabling the MBI, Port 6 must be placed in in-
put mode by writing 0016 to P6D (001516).
When data is written to the MCU from the master
CPU, an input buffer full interrupt request occurs.
Similarly, when data is read from the master CPU, an
output buffer empty interrupt request occurs.
When the bus interface is operating, DQ0-DQ7 be-
come a 3-state data bus that sends and receives
data, command, and status to and from the master
CPU. At the same time, W, R, S0, S1, and A0 become
host CPU control signal input pins.
The two input buffer full interrupt requests and two out-
put buffer full requests are multiplexed as shown in
Figure 1.76.
The bus interface can be operated under normal
MCU control or under on-chip DMA control for fast
data transfer. If a master CPU has a large amount of
data to be transferred, use of the on-chip DMA con-
troller is highly recommended.
The bus interface signal input level can be pro-
grammed as CMOS level (default) or as TTL level.
Bit7 of the Port Control Register (PTC7) is used for the
input level selection.
OBF0 IBF0 A0 S0 R W
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
System Bus
W R S1 A0 IBF1OBF1
b7
U7
U6
U5
U4
A00
U2
b1
IBF0
b0
OBF0
b0
RD
WR
DBB0
RD
WR
DBB1
DBBS0 DBBS1
b7
U7
U6
U5
U4
A01
U2
IBF1
OBF1
b0
Fig. 1.75. Bus Interface Circuit
Data Bus
Input buffer full flag 0
IBF0
Input buffer full flag 1
IBF1
Output buffer full flag 0
OBF0
Output buffer full flag 1
OBF1
IBF0
IBF1
IBF
OBF0
(OBE0)
OBF1
(OBE1)
OBE
Rising Edge
detection circuit
Rising Edge
detection circuit
Rising Edge
detection circuit
Rising Edge
detection circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
Input Buffer full interrupt
request signal IBF
Output Buffer Empty interrupt
request signal OBE
Set interrupt request at this rising edge
Set interrupt request at this rising edge
Fig. 1.76. Data Bus Buffer Interrupt Request Circuit
b1
b0
65
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