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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.21.2 USB Interrupts

There are two types of USB interrupts in this device.

USB function (including overrun/underrun, reset, sus-

pend and resume) interrupt, which is used to control

the flow of data.

The second type is start-of-frame (SOF) interrupt,

which is used to monitor the transfer of isochronous

(ISO) data.

1.21.2.1 USB Function Interrupts

Endpoints 1-4 each have two interrupt status flags as-

sociated with them to control data transfer or to report

a STALL/UNDER_RUN/OVER_RUN condition. The

USB Endpoint x Out Interrupt Status Flag is set when

the USB FCU successfully receives a packet of data,

or the USB FCU sets the FORCE_STALL bit or the

OVER_RUN bit of the Endpoint x OUT CSR. The

USB Endpoint x In Interrupt Status Flag is set when

the USB FCU successfully sends a packet of data or

sets the UNDER_RUN bit of the Endpoint x IN CSR.

Endpoint 0 (the control endpoint) has one interrupt

status bit associated with it to control data transfer or

report a STALL condition. The USB Endpoint 0 Inter-

rupt Status Flag is set when the USB FCU

successfully receives/sends a packet of data, sets the

SETUP_END bit or the FORCE_STALL bit, or clears

the DATA_END bit in the Endpoint 0 IN CSR. Each

endpoint interrupt is enabled by setting the corre-

sponding bit in the USB Interrupt Enable Register 1

and 2 (see Figure 1.57 and Figure 1.58). The USB In-

terrupt Status Register 1 and 2, shown in Figure 1.55

and Figure 1.56, are used to indicate pending inter-

rupts for a given endpoint. The USB FCU sets the

interrupt status bits. The CPU writes a “1” to clear the

corresponding status bit. By writing back the same

value it read, the CPU will clear all the existing inter-

rupts. The CPU must read then write both status

registers, writing status register 1 first and status reg-

ister 2 second to guarantee proper operation.

The Suspend Signaling Interrupt Status Flag is set if

the USB FCU does not detect any bus activity on D+/

D- for at least 3ms. The Resume Signaling Interrupt

Status Flag is set when a USB FCU is in the suspend

state and detects non-idle signaling on D+/D-. There

is an interrupt enable bit for the suspend interrupt (bit

7 of Interrupt Enable Register 2), but not one for the

resume interrupt. The resume interrupt is always en-

abled.

The USB Reset Interrupt Status Flag is set if the USB

FCU sees a SE0 present on D+/D- for at least 2.5ms.

When this bit is set, all USB internal registers (except

for this bit) are reset to their default values. This bit is

cleared by the CPU writing a “1” to it. When the CPU

detects a USB reset interrupt, it needs to re-initialize

the USB FCU in order for it to accept packets from

the host. The USB reset interrupt is always enabled.

The Overrun/Underrun Interrupt Status Flag is set

(applicable to endpoints used for isochronous data

transfer) when an overrun condition occurs in an end-

point (CPU is too slow to unload the data from the

FIFO), or when an underrun condition occurs in an

endpoint (CPU is too slow to load the data to the

FIFO).

The USB Function Interrupt (sum of all individual

function interrupts) is enabled by setting bit 0 of Inter-

rupt Control Register A (ICONA) to a “1”.

1.21.2.2 USB SOF Interrupt

The USB SOF (Start-Of-Frame) interrupt is used to

control the transfer of isochronous data. The USB

FCU generates a start-of-frame interrupt when a

start-of-frame packet is received. The USB SOF inter-

rupt is enabled by setting bit 1 of ICONA to a “1”.

1.21.3 USB Endpoint FIFOs

The USB FCU has an IN (transmit) FIFO and an OUT

(receive) FIFO for each endpoint. Each endpoint (ex-

cept endpoint 0) can be configured to support both

single packet mode (only a single data packet is al-

lowed to reside in the endpoint’s FIFO) or dual packet

mode (up to two data packets are allowed to reside in

the endpoint’s FIFO), which provides support for

back-to-back transmission or back-to-back reception.

The mode configuration is automatically set by the

MAXP value. When MAXP > 1/2 of the endpoint’s

FIFO size, single packet mode is set. When MAXP <=

1/2 of the endpoint’s FIFO size, dual packet mode is

set.

Throughout this specification, the terms “IN FIFO”

and “OUT FIFO” refer to the FIFOs associated with

the current endpoint as specified by the Endpoint In-

dex Register.

In the event of a bad transmission/reception, the USB

FCU handles all the read/write pointer reversal and

data set management tasks when it is applicable.

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