GF9105A 데이터 시트보기 (PDF) - Unspecified

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GF9105A

Component Digital Transcoder

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GF9105A DETAILED DEVICE DESCRIPTION

INPUT/OUTPUT DATA PORTS

The GF9105A has 8 bi-directional data ports, labelled P1 to P8. P1 to P3 and P5 to P7 are 13-bit data ports while P4 and P8

are 11-bit data ports. The OUTPUT/INPUT control bit and the HVF_OUT control bit (See Host Programming Section and

figures 4a - 4d) control how P1 to P8 are configured.

When OUTPUT/INPUT is set low and when HVF_OUT is set low, P112..0, P212..0, P312..0, P410..0 are configured as input video

data ports and P512..0, P612..0, P712..0, P810..0 are configured as output video data ports (refer to Figure 4a).

When OUTPUT/INPUT is set low and when HVF_OUT is set high, P111..0, P211..0, P311..0, P410..0 are configured as input video

data ports and P512..0, P612..0, P712..0, P810..0 are configured as output video data ports. In this mode, P112, P212, P312 are

configured as outputs for H, V, and F output data. P112 carries H data, P212 carries V data and P312 carries F data (refer to

Figure 4c).

When OUTPUT/INPUT is set high and when HVF_OUT is set low, P112..0, P212..0, P312..0, P410..0 are configured as output

video data ports and P512..0, P612..0, P712..0, P810..0 are configured as input video data ports (refer to Figure 4b).

When OUTPUT/INPUT is set high and when HVF_OUT is set high, P111..0, P211..0, P311..0, P410..0 are configured as output

video data ports and P512..0, P612..0, P712..0, P810..0 are configured as input video data ports. In this mode, P112, P212, P312

are configured as outputs for HVF output data. P112 carries H data, P212 carries V data and P312 carries F data (refer to

Figure 4d).

Note: No bi-directional I/Os should be driven until after the OUTPUT/INPUT and the HVF_OUT control bits have been set

(unless DP_EN is set high to tri-state the outputs). This will ensure that any potential conflicts between input and output data

buses are avoided.

OUTPUT/INPUT AND HVF CONTROL BIT

OUTPUT/INPUT

HVF_OUT

DESCRIPTION

0

0

P112..0, P212..0, P312..0, P410..0 are configured as input video data ports.

P512..0, P612..0, P712..0, P810..0 are configured as output video data ports.

Refer to Figure 4a.

0

1

P111..0, P211..0, P311..0, P410..0 are configured as input video data ports.

P112, P212, P312 are configured as H, V and F outputs, respectively.

P512..0, P612..0, P712..0, P810..0 are configured as output video data ports.

Refer to Figure 4c.

1

0

P112..0, P212..0, P312..0, P410..0 are configured as output video data ports.

P512..0, P612..0, P712..0, P810..0 are configured as input video data ports.

Refer to Figure 4b.

1

1

P111..0, P211..0, P311..0, P410..0 are configured as output video data ports.

P112, P212, P312 are configured as H, V and F outputs, respectively.

P512..0, P612..0, P712..0, P810..0 are configured as input video data ports.

Refer to Figure 4d.

For H, V, F output timing refer to the Timing Reference Signal Section of this data sheet.

521 - 88 - 03

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