GF9105A 데이터 시트보기 (PDF) - Unspecified
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GF9105A Datasheet PDF : 37 Pages
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OUTPUT/INPUT = 0, HVF_OUT = 1
13 BIT PHYSICAL INTERFACE
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
Embedded 10 bit signal
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V, or F 0
output
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P410..0
Embedded 10 bit signal
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P112..0 to P312..0
Embedded 8 bit signal
H, V, or F 0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
output
Input Port: P410..0
Embedded 8 bit signal
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
13 BIT PHYSICAL INTERFACE
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
13 BIT PHYSICAL INTERFACE
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
(refer to Figures 4a and 4c). While OUTPUT/INPUT=1 Processing Core port C1 corresponds to device data port P5 (Refer to
Figures 4b and 4d).
The KEY:2:2 or KEY:XX:XX data enters the GF9105A Processing Core from Processing Core input port C4. While OUTPUT/
INPUT=0, Processing Core port C4 corresponds to device data port P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1, Processing Core port C4 corresponds to device data port P8 (Refer to Figures 4b and 4d).
When MUXED_IN is set high, input data is assumed to be 4:2:2:4 or 4:4:4:4 data in a non-multiplexed format as shown in
Figure 7c. Since the incoming data is already non-multiplexed, the input data is passed on to the next processing section
unmodified. In this mode of operation, input data is presented to all four Processing Core input ports. While OUTPUT/
INPUT=0, Processing Core ports C1-C4 correspond to device data ports P1-P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1 Processing Core ports C1-C4 correspond to device data ports P5-P8 (Refer to Figure 4b and 4d).
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