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AN-136

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

Integrated Device Technology 

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

APPLICATION NOTE AN-136

The 71215/16 is shown in more detail in Figure 4. The tag

memory is controlled by the Write Enable Tag (WET) and

Output Enable Tag (OET) pins. During writes, WET is synchro-

nous to CLK, as are the input data (TAG0 - TAG11) and

address (A0 - A13). Note that WET has no effect on the TAG

output buffers, so OET must be high to disable the outputs

during writes. Reads are performed by deasserting WET and

asynchronously asserting OET. For cache architectures in

which the tag is never read (e.g. write-through caches), OET

may be tied to VCC. When both WET and OET are high, the

71215/16 is in the match mode, where the TAG0 - TAG11

inputs are compared with the stored data and are used to

generate the MATCH and BRDY/TA outputs. In both read and

match modes, the address path is flow-through for the fastest

possible response to a new address.

The three status bits of the 71215/16 are labeled VLD/S1,

DTY/S2, and WT/S3. The reason for the dual names is that

their functions vary, dependent on the state of the static Status

Function (SFUNC) input signal. When SFUNC is low, the

status bits are said to be in a “dedicated” mode and are

referred to as Valid, Dirty and Write-Through. See Figure 5.

When SFUNC is high, the status bits play no special role within

the 71215/16 and are simply referred to as Status 1, Status 2

and Status 3. See Figure 6. The functionality of VLD and WT

in the dedicated mode is described later. DTY/S2 does not

have any special functionality within the 71215/16.

WTIN / S3IN

DTYIN / S2IN

VLDIN / S1IN

I/O

Address

MEMORY V D WP

WET

WES

internal RESET

OE

COMPARE

WTOUT / S3OUT

DTYOUT / S2OUT

VLDOUT / S1OUT

CLK

71216 only

W/R (TT1)

BRDYH (TAH)

BRDYIN(TAIN)

BRDYOE (TAOE)

Figure 5. Dedicated Mode Logic (71216 pin names are in parenthesis)

5

MATCH

BRDY (TA)

3176 drw 05

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