AN-136 데이터 시트보기 (PDF) - Integrated Device Technology
부품명
상세내역
일치하는 목록
AN-136 Datasheet PDF : 12 Pages
| |||
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
ADDR A0 - A28
PowerPC
TT1
TA
A12
A13 - A26
(2) IDT71216
TAG RAM
A0 - A11
TAG (11:0)
ADDR (13:0)
MATCH
RESET
3
STATUSout
TT1
TA
VCC
3
STATUSin
TAOE
TAH
TAIN
CS2
WES
CS1
OES
SFUNC
WET
OET
PWRDN
CS2
CS1
VARIOUS CONTROL SIGNALS
DATA
DH0 - DH31, DL0 - DL31, and DP0 - DP7
CHIP SET
MATCH
STATUS
STATUS
TAOE
TAH
WES
WET
OET
PWRDN
TA
A12
A13 - A28
VCC
ADDR
CS2
CS1
64K x 18
BURST
SRAM
I/Os
ADDR
CS2
CS1
CACHE READ
and WRITE
64K x 18
BURST
SRAM
I/Os
MAIN MEMORY READ/WRITE
Figure 13: PowerPC / 71216 Example of 1 MB Cache
3176 drw 13
Figure 13 shows a 1MB cache for the PowerPC using the
71216. The implementation is essentially the same as for
512KB, but with two 71216 Tags and two banks of data
SRAMs. Except for CS1 and CS2, all the same signals that
were connected to the first Tag RAM should be connected to
the same pins of the second Tag RAM. The least significant
tag bit of the 512KB cache is used to select between the two
Tag RAMs of the 1MB cache. The same is true for the two
banks of data SRAMs. The tag field then shifts one bit in the
direction of the more significant address bits. Please note that
the PowerPC and Intel processors do not have the same
address sequence. A0 is the MSB for the PowerPC while A31
is the MSB for Intel's processors.
It is also possible to double the size of the cache and
cached address space without doubling up the Tag RAMs.
This can be done by doubling the line size of the cache - from
32 bytes to 64 bytes, for example. It is not necessary to have
the same line size for both the primary and secondary caches,
though it does simplify the cache controller. A more detailed
discussion of this topic is beyond the scope of this application
note.
The CLK pin should be driven by the same clock that drives
the CPU. Although there is no standard for clock skew
tolerances between devices, a recommended target is ±1nS.
MESI PROTOCOL IMPLEMENTATION
MESI is a cache coherency protocol, implemented in the
primary cache of both the PowerPC 601 and the Pentium
Processor. With the 71215/16, it is now practical to also
implement MESI for the L2 cache. The acronym stands for
Modified (write-back data that is dirty), Exclusive (clean write-
back data that can later transition to Modified), Shared (write-
through data which cannot become Modified) and Invalid. In
short, it allows for cache lines to be individually marked as
11
Share Link: 