AN-136 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

일치하는 목록

AN-136

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

Integrated Device Technology 

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

APPLICATION NOTE AN-136

ADDR(0:13)

OET

TAG (0:11)

16K x 12

MEMORY

16K x 3

MEMORY

VLDOUT

DLYOUT

WTOUT

WET

WES

VLDin / S1IN

DLYin / S2IN

WTin / S3IN

BRDYIN (TAIN)

RESET

CLK

SFUNC

BRDYH (TAH)

W/R (TT1)

BRDYOE (TAOE)

MATCH AND

BRDY LOGIC

OES

MATCH

BRDY (TA)

CS1

CS2

PWRDN

CONTROL

LOGIC

Chip enabling

Reseting the 16K x 3 memory

Powering down

Disabling outputs

3176 drw 03

Figure 3. Simplified 71215 / 71216 Block Diagram (71216 signal names are in parenthesis)

With a 16K x 12 tag memory, the 71215 and 71216 are

wider and deeper than most Tag RAMs. For a typical 64-bit

CPU with a 32-byte line size, the 16K depth supports a 512KB

cache while the 12-bit tag field supports 2GB of cacheable

main memory. Thus, only a single component is required for

most applications. Table 1 shows the relationships between

Tag RAM size, cache size, and cacheable main memory size.

The Tag depth is equal to the cache size divided by the line

size. The Tag width is equal to the base-2 log of the ratio of

main memory size to cache size.

TABLE 1: REQUIRED TAG RAM SIZE AS A

FUNCTION OF CACHE SIZE AND MAIN

MEMORY SIZE (For 32-byte line size and direct

mapped cache architecture.)

For a 1MB cache and 4GB of cacheable main memory, two

of the devices may be cascaded in depth without any timing

penalty apart from increased capacitive loading. This is

accomplished with the two Chip Select pins. A low order

address signal may be connected to CS1 on one chip and to

CS2 on the other so that at any given time, one is selected and

the other is deselected. The deselected chip ignores all

control inputs (except RESET and PWRDN) and tri-states its

outputs so that the two chips can be conveniently bussed

together. As expected, worst case timing delays from the Chip

Select inputs are the same as for the Address inputs. When

only a single 71215 or 71216 is used in an application, CS1 is

tied to VSS and CS2 is tied to VCC.

Cache Size

64MB

128KB 4K x 9

256KB 8K x 8

512KB 16K x 7

1MB

32K x 6

Cacheable Main Memory Size

256MB 1GB

2GB

4GB

4K x 11 4K x 13 4K x 14 4K x 15

8K x 10 8K x 12 8K x 13 8K x 14

16K x 9 16K x 11 16K x 12 16K x 13

32K x 8 32K x 10 32K x 11 32K x 12

3176 tbl 01

3

Share Link: