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AD1836AASZ

Multichannel 96 kHz Codec

Analog Devices 

AD1836A

Data Sheet

Table 11. Pin Function Changes in AUX Mode

Pin Name (I2S/AUX Mode)

I2S Mode

ASDATA1(O)

I2S Data Out, Internal ADC1

ASDATA2(O)/DAUXDATA(O) I2S Data Out, Internal ADC2

DSDATA1(I)

I2S Data In, Internal DAC1

DSDATA2(I)/AAUXDATA(I)

I2S Data In, Internal DAC2

DSDATA3(I)/AAUXDATA2(I) I2S Data In, Internal DAC3

ALRCLK(O)

LRCLK for Internal ADC1, ADC2

ABCLK(O)

BCLK for Internal ADC1, ADC2

DLRCLK(I)/AUXLRCLK(I/O)

LRCLK In/Out Internal DACs

DBCLK(I)/AUXBCLK(I/O)

BCLK In/Out Internal DACs

AUX Mode

TDM Data Out, to SHARC

AUX—I2S Data Out (to External DAC)

TDM Data In, from SHARC

AUX—I2S Data In 1 (to External ADC)

AUX—I2S Data In 2 (to External ADC)

TDM Frame Sync Out, to SHARC

TDM BCKL Out, to SHARC

AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).

In master mode, driven by internal MCLK/512.

AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).

In master mode, driven by internal MCLK/8.

ADC

AUXBCLK

AUXLRCLK

AUXDATA2

I2S

DECODE

AUXDATA1

SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO

RESET INTERNAL ADC COUNTER

SYNC

4 ADCS

SPORT

LRCLK

ABCLK

ASDATA1

ALRCLK

ABCLK

ASDATA1

DATA TO SHARC

MCLK

ASDATA1

I2S

TIMING GEN

LRCLK BCLK

FROM SHARC

DSDATA1

FROM EXT A/D DSDATA2/AUXDATA1

FROM EXT A/D DSDATA3/AUXDATA2

DLRCLK/AUXLRCLK

DBCLK/AUXBCLK

MASTER/SLAVE MODE,

FROM ADC SPI PORT

DSDATA1

DSDATA2

DSDATA3

AUXDATA

MUX

I2S FORMATTER

ASDATA2/DAUXDATA

DATA TO EXT DAC

BCLK AND LRCLK FOR

EXT DAC COMES FROM

ADC BCLK, LRCLK.

MUST BE IN I2S MODE.

AUXLRCLK AUXBCLK

2 AUX

CHANNELS

LRCLK

BCLK

MUX

MUX

SPORT

6 MAIN

CHANNELS

DAC

INDICATES MUX POSITION FOR AUX-TDM MODE

6-CH

DAC

Figure 12. Extended TDM Mode (Internal Flow Diagram)

Rev. A | Page 18 of 24

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