AD1836AASZ 데이터 시트보기 (PDF) - Analog Devices
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AD1836AASZ Datasheet PDF : 24 Pages
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AD1836A
Data Sheet
FSTDM
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA1
DSDATA1
TDM (IN)
DSDATA1
MSB TDM
1ST
CH
MSB TDM
8TH
CH
INTERNAL
ADC L0
32
MSB TDM
1ST
CH
INTERNAL
ADC L1
AUX_ADC L0 AUX_ADC L1
INTERNAL
ADC R0
INTERNAL
ADC R1
AUX_ADC R0 AUX_ADC R1
MSB TDM
8TH
CH
INTERNAL
DAC L0
32
INTERNAL
DAC L1
INTERNAL
DAC L2
AUX_DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUX_DAC R0
AUX
LRCLK I2S
(FROM AUX ADC NO. 1)
AUX
BCLK I2S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
LEFT
I2S––MSB LEFT
I2S––MSB LEFT
RIGHT
I2S––MSB RIGHT
I2S––MSB RIGHT
DAUXDATA (OUT)
(TO AUX DAC)
I2S––MSB LEFT
NOTE
AUX BCLK FREQUENCY IS 64 × FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE.
FSTDM FOLLOWS AUX LRCLK BY 3 1/2 ± 1/2 TDM BCLK IN BOTH MASTER AND SLAVE MODES.
Figure 9. AUX Mode Timing (Note that the Clocks Are Not to Scale)
I2S––MSB RIGHT
Rev. A | Page 16 of 24
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