NXP Semiconductors
TDF8599
Class-D power amplifier with load diagnostics
OUT1P
OUT1N
master
OUT2P
OUT2N
phase
0
π
OUT1P
OUT1N
slave
OUT2P
1/2 π
OUT2N
Fig 13. Master and slave operation with 1⁄2 π phase shift.
3/2 π
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8.4.3 Parallel mode
In Parallel mode; the two output stages operate in parallel to enlarge the drive capability.
The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board
(PCB) as shown in Figure 14. The parallel connection can be made after the output filter,
as shown in Figure 14 or directly to the device output pins.
+
IN1P
−
IN1N
OUT1N
−
OUT1P
IN2N
TDF8599
IN2P
MOD
OUT2P
+
OUT2N
RMOD
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Fig 14. Mono and Parallel modes
In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.
However, clip detection must be deactivated by disabling clip detection for both channel 1
and channel 2.
TDF8599_1
Product data sheet
Rev. 01 — 13 November 2008
© NXP B.V. 2008. All rights reserved.
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