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TDF8599

I2C-bus controlled dual channel 43 W/2Ωsingle channel 85 W/1Ω class-D power amplifier with load diagnostics

NXP Semiconductors. 

NXP Semiconductors

TDF8599

Class-D power amplifier with load diagnostics

directly. Values for CPLL_s, CPLL_p and RPLL depend on the desired loop bandwidth

(BWPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BWPLL Ω. The corresponding values for

CPLL_s and CPLL_p are given by:

CPLL_p = -R---P----L--L--0--×-.--0--B-3---2W------P---L---L- [F ]

(3)

Remark: CPLL_P is only needed when π/4 phase shift is selected. See Section 8.4.2 for

more detailed information.

CPLL_s = -R---P----L--L----×-0---.-B-8---W------P---L---L-[F ]

(4)

When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,

the PLL loop bandwidth BWPLL should be 100 × fSSM.

100 µA

OSCSET

100 µA

OSCSET

SSM

PLL

PLL

SSM

CPLL_s

RPLL

CPLL_P(1)

001aai776

001aai777

a. Off

Fig 9. Phase lock operation

b. On

See Table 7 for all oscillator modes.

Table 7. Oscillator modes

OSCSET pin OSCIO pin

Rosc > 26 kΩ

Rosc > 26 kΩ

Rosc = 0 Ω

Rosc = 0 Ω

output

output

input

input

SSM pin

Cssm

shorted to AGND

CPLL + RPLL

shorted to AGND

Oscillator modes

master, spread spectrum

master, no spread spectrum

slave, PLL enabled

slave, PLL disabled

8.4 Operation mode selection

Pin MOD is used to select specific operation modes. The resistor (RMOD) connected

between pins MOD and AGND determines the operation mode. The mode of operation

depends on whether non-I2C-bus mode or I2C-bus mode is active. This is in turn

determined by the resistor value connected between pins ADS and AGND.

TDF8599_1

Product data sheet

Rev. 01 — 13 November 2008

© NXP B.V. 2008. All rights reserved.

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