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IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

COMMERCIAL TEMPERATURE RANGE

alone configuration BiFIFOs connected to a peripheral.

In a 36- to 9-bit configuration, the master device controls

the bus. The Port B interface pins of the master device are

outputs and the interface pins of the slave device are inputs.

A 36- to 9-bit configuration of two BiFIFOs connected to a

peripheral is shown in Figure 4.

Port A Interface

The BiFIFO is straightforward to use in microprocessor-

based systems because each BiFIFO port has a standard

microprocessor control set. Port A has access to six re-

sources: the A→B FIFO, the B→A FIFO, the 9-bit direct data

bus (bypass path), the configuration registers, status and

command registers. The Port A Address and Read/Write pins

determine the resource being accessed as shown in Table 1.

Data Strobe is used to move data in and out of the BiFIFO.

When either of the internal FIFOs are accessed 18 bits of

data are transferred across Port A. Since the bypass path is

only 9 bits wide, the least significant byte with parity

(DA0-DA7, DA16) is used on Port A. All of the registers are 16

bits wide which means only the data bits (DA0-DA15) are

passed by Port A.

36-BIT PROCESSOR to 9-BIT PROCESSOR CONFIGURATION

Processor

A

Address

Control

Data

RAM

IDT

BiFIFO

(Master)

Cntl A Cntl B

ACK

REQ

CLK

Data A Data B

IDT

BiFIFO

(Slave)

Cntl A Cntl B

ACK

REQ

CLK

Data A Data B

18

Processor

B

Control

Data

RAM

2669 drw 06

Figure 3. 36- to 9-Bit Processor Interface Configuration

NOTE:

1. Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and DSB or RB and WB.

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