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IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

PIN DESCRIPTIONS

Symbol

ACK

Name

Acknowledge

CLK

FLGA-FLGD

Clock

Flags

RS

VCC

GND

Reset

Power

Ground

COMMERCIAL TEMPERATURE RANGE

I/O

Description

O

When Port B is programmed in peripheral mode, Acknowledge is

asserted in response to a Request signal. This confirms that a data

transfer may begin. Acknowledge can be programmed either active

HIGH or active LOW.

I

This pin is used to generate timing for ACK, RB, WB,

DSB and R/WB when Port B is in the peripheral mode.

O

These four outputs pins can be assigned to any one of the eight

internal flags in the BiFIFO. Each of the two internal FIFOs (A-to-B

and B-to-A) has four internal flags: Empty, Almost-Empty, Almost-

Full, and Full. If parity checking is enabled, the FLGA pin can also

be assigned as a parity error output.

I

A LOW on this pin will perform a reset of all BiFIFO functions.

Software reset can be achieved through command register.

There are two +5V power pins on all four devices.

There are four ground pins

2669 tbl 02

5.31

4

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