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IDT72510L25J
Integrated Device Technology
IDT72510L25J Datasheet PDF : 32 Pages
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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION REGISTER 7 FORMAT
BIT
0-7
8
9
10
11
12-15
FUNCTION
Unused
Parity Input Control
0 Disable Parity Generate, Enable Parity Check
B→A
1 Enable Parity Generate, Disable Parity Check
Parity Output Control
0 Disable Parity Generate, Enable Parity Check
A→B
1 Enable Parity Generate, Disable Parity Check
Parity Odd/Even
0 Odd
Control
1 Even
Assign Parity Error to
0 No Parity Error Output
Flag A Pin
1 Parity Error on Flag A Pin
Unused
2669 tbl 16
Table 12. BiFIFO Configuration Register 7 Format
bits go to the LSB (DA0-DA7, DA16) or the MSB (DA8-DA15, DA17)
of Port A. This data ordering is controlled by bit 1 of Configu-
ration Register 5 (see Table 11).
DMA Control Interface
The BiFIFO has DMA control to simplify data transfers with
peripherals. For the BiFIFO DMA controls (REQ, ACK and
CLK) to operate, the BiFIFO must be in peripheral interface
mode (Configuration Register 5, Table 11).
DMA timing is controlled by the external clock input, CLK.
An internal clock is derived from this CLK signal to generate
the RB, WB, DSB and R/WB output signals. The internal clock
also determines the timing between REQ assertion and ACK
assertion. Bit 9 of Configuration Register 5 determines whether
the internal clock is the same as CLK or whether the internal
clock is CLK divided by 2.
Bit 8 of Configuration Register 5 sets whether RB, WB and
DSB are asserted for 1 or 2 internal clocks. Bits 6 and 7 of
Configuration Register 5 set the number of clocks between
REQ assertion and ACK assertion. The clocks between REQ
assertion and ACK assertion can be 2, 3, 4 or 5.
Bits 4 and 5 of Configuration Register 5 set the polarity of
the REQ and ACK pins, respectively.
A DMA transfer command sets the Port B read/write direc-
tion (see Table 5). The timing diagram for DMA transfers is
shown in Figure 17. The basic DMA transfer starts with REQ
assertion. After 2 to 5 internal clocks, ACK is asserted by the
BiFIFO. ACK will not be asserted if a read is attempted on an
Empty A→B FIFO or if a write is attempted on a Full B→A FIFO.
If the BiFIFO is in Motorola-style interface mode, R/WB is set
at the same time that ACK is asserted. One internal clock later,
DSB is asserted. If the BiFIFO is in Intel-style interface mode,
either RB or WB is asserted one internal clock after ACK
assertion. These read/write controls stay asserted for 1 or 2
internal clocks, then ACK, DSB, RB and WB are made inactive.
This completes the transfer of one 9-bit word.
On the next rising edge of CLK, REQ is sampled. If REQ is
still asserted, another DMA transfer starts with the assertion
of ACK. Data transfers will continue as long as REQ is
asserted.
Parity Checking and Generation
Parity generation or checking is performed by the BiFIFO
on data passing through Port B. Parity can either be odd or
even as determined by Bit 10 of Configuration Register 7.
When parity checking is enabled, DB8 is treated as a data
bit. DB8 data will be passed to DA16 (bypass operation) or stored
in the RAM array (FIFO operation) for B->A operation; similarly,
DA16 or parity bits from the RAM array will be passed to DB8
for A->B operations. A->B read parity errors and B->A write
parity errors are shown in Bit 9 and 10 in the Status Register.
If an external parity error signal is required, a logical OR of the
INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO
From
To
Empty Flag
Almost-Empty Flag Almost-Full Flag
0
0
Asserted
Asserted
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
n+1
D - (m + 1)
Not Asserted
Not Asserted
Not Asserted
D-m
D-1
Not Asserted
Not Asserted
Asserted
D
D
Not Asserted
Not Asserted
Asserted
NOTE:
1. BiFIFO flags can be assigned to external flag pins to be observed. D = FIFO depth (IDT72510 = 512, IDT72520 = 1024),
n = Almost-Empty flag offset, m = Almost-Full flag offset.
Table 13. Internal Flag Truth Table.
Full Flag
Not Asserted
Not Asserted
Not Asserted
Not Asserted
Asserted
2669 tbl 17
5.31
15
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