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IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

COMMERCIAL TEMPERATURE RANGE

Port B Interface

Port B also has parity, reread/rewrite and DMA functions.

Port B can be configured to interface to either Intel-style (RB,

WB) or Motorola-style (DSB, R/WB) devices in Configuration

Register 5 (see Table 11). Port B can also be configured to talk

to a processor or a peripheral device through Configuration

Register 5. In processor interface mode, the Port B interface

controls are inputs. In peripheral interface mode, the Port B

interface controls are outputs. After a hardware reset or a

software Reset All command, Port B defaults to an Intel-style

processor interface; the controls are inputs.

Two 9-bit words are put together to create each 18-bit word

stored in the internal FIFOs. The first 9-bit word written to Port

B goes into the Odd Byte Register shown in the detailed block

diagram. The Odd Byte Register valid bit (Bit 8) in the Status

Register is 1 when this first 9-bit word is written. The data bits

from Port B (DB0-DB7) are also stored in the lower 8 bits of the

Status Register when Status Register format 0 is selected

(see Table 8). The second write on Port B moves the 9-bits

from Port B and the 9-bits in the Odd Byte Register into the

B→A FIFO and advances the B→A Write Pointer. The Status

Register valid bit is set to 0 after the second write.

When Port B reads data from the A→B FIFO, two buffers

choose which 9 of the 18 memory bits are sent to Port B.

These buffers alternate between the upper 9 bits (DA8-DA15,

DA17) and the lower 9 bits (DA0-DA7, DA16). The A→B Read

Pointer is advanced after every two Port B reads.

The BiFIFO can be set to order the 9-bit data so the first 9-

CONFIGURATION REGISTER 5 FORMAT

Bit

Function

0

Select Port B Interface

0

Pins are RB and WB (Intel-style interface)

RB & WB or DSB & R/WB

1

Pins are DSB and R/WB (Motorola-style interface)

1

Byte Order of 18-bit Word

0

Lower byte DA7-DA0 and parity DA16 are read or written first on Port

B

1

Upper byte DA15-DA8 and parity DA17 are read or written first on

Port B

2

Full Flag Definition

0 Full Flag is asserted when write pointer meets read pointer

1 Full Flag is asserted when write pointer meets reread pointer

3

Empty Flag Definition

0 Empty Flag is asserted when read pointer meets write pointer

1 Empty Flag is asserted when read pointer meets rewrite pointer

4

REQ Pin Polarity

0 REQ pin active HIGH

1 REQ pin active LOW

5

ACK Pin Polarity

0 ACK pin active LOW

1 ACK pin active HIGH

00 2 internal clocks between REQ assertion and ACK assertion

7-6

REQ / ACK Timing

01 3 internal clocks between REQ assertion and ACK assertion

10 4 internal clocks between REQ assertion and ACK assertion

11 5 internal clocks between REQ assertion and ACK assertion

8

Port B Read and Write

0

RB, WB, and DSB are asserted for 1 internal clock

Timing Control for Peripheral Mode

1

RB, WB, and DSB are asserted for 2 internal clocks

9

Internal Clock

0 internal clock = CLK

Frequency Control

1 internal clock = CLK divided by 2

10

Port B Interface

0 Processor interface mode (Port B controls are inputs)

Mode Control

1 Peripheral interface mode (Port B controls are outputs)

00 Stand-alone mode (18- to 9-bits, 36- to 18-bits)

12-11

Width Expansion

Mode Control

01 Reserved

10 Slave width expansion mode (36- to 9-bits)

11 Master width expansion mode (36- to 9-bits)

13

Unused

14

Unused

15

Unused

Table 11. BiFIFO Configuration Register 5 Format

2669 tbl 15

5.31

14

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