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M37640E8

Single-Chip 8-BIT CMOS Microcontroller M37640E8-XXXFP Specification

MITSUBISHI ELECTRIC  

7600 Series

M37640E8-XXXF Preliminary Specification

Mitsubishi Microcomputers

2.3 Oscillator Circuit

2.3.1 Description

An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for

operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for

oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. A

flow diagram for the oscillator circuit is shown in Figure 2-6 and a block diagram of the oscillator

circuit is shown in Figure 2-7. The following external clock inputs are supported:

• A quartz crystal oscillator of up to 24 MHz, connected to the Xin and Xout pins.

• An external clock signal of up to 48 MHz, connected to the Xin pin.

• A ceramic resonator or quartz crystal oscillator of 32.768 kHz, connected to the XCin and XCout

pins.

• An external clock signal of up to 5.12 MHz, connected to the XCin pin.

The frequency synthesizer can be used to generate a 48MHz clock signal (fUSB) needed by the USB

block and clock fSYN, which can be chosen as the source for the system and peripheral clocks. Both

fUSB and fSYN are phase-locked frequency multiples of the frequency synthesizer input. The inputs to

the frequency synthesizer can be either Xin or XCin.

The two-phase non-overlapping system clock (CPU and peripherals) is derived from the source to the

clock circuit and is 1/2 the frequency of the source. (i.e. Source = 24 MHz, system clock = 12 MHz)

Any one of four clock signals can be chosen as the source for the system and peripheral clocks; fXin/

2, fXin, fXCin, or fSYN. The selection is based on the values of bits CPMA6, CPMA7 and CCR7. The

default source after reset is fXin/2.

The default source for the system and peripheral clocks is fXin/2. If fXin = 24MHz, then the CPU

will be running at Φ = 6MHz (low frequency mode. For the CPU to run in high frequency mode, i.e.,

source of clock = fXin, write a “1” to bit 7 of the clock control register.

MSB

7

CCR7

CCR6

Bits 0-3

CCR4:

CCR5:

CCR6:

CCR7:

CCR5

CCR4

Reserved

Reserved

Reserved

Reserved

LSB

0

Reserved (Read/Write “0”)

PLL Bypass Bit (bit 4)

0: fUSB = fVCO (Frequency synthesizer output)

1: fUSB = fXin

XCout Oscillation Drive Disable Bit (bit 5)

0: XCout oscillation drive is enabled (when XCin oscillation is enabled).

1: XCout oscillation drive is disabled.

Xout Oscillation Drive Disable Bit (bit 6)

0: Xout oscillation drive is enabled (when Xin oscillation is enabled).

1: Xout oscillation drive is disabled.

Xin Divider Select Bit (bit 7)

0: fXin/2 is used for the system clock source when CMPA7:6=00

1: fXin is used for the system clock source when CMPA7:6=00

Figure 2-5. Clock Control Register

Address: 001F16

Access: R/W

Reset: 0016

The drive strength of the Xout and XCout inverting amplifier can be controlled by bits CPMB7 and

CPMA3, respectively. High drive is the default at reset or after executing a STP instruction and must

be chosen whenever restarting Xin or XCin oscillation if a ceramic or crystal oscillator is used. When

oscillation has been established, low drive can be selected to reduce power consumption. If an

external clock signal is input to Xin or XCin, the inverting amplifiers can be disabled by means of the

CCR6 and CCR7 bits, respectively, in order to reduce power consumption.

2-8

7/9/98

Oscillator Circuit

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