M37640E8 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
Main Routine
Interrupt Request
(Note 1)
.......
.......
M(S)
(PCh)
(S)
Return Address Stored
on Stack (Note 2)
M(S)
(S-1)
(PCl)
(S)
(S-1)
Subroutine
Execute JSR
.......
M(S)
(PCh)
(S)
M(S)
(S-1)
(PCl)
Return Address Stored
on Stack (Note 2)
(S)
M(S)
(S)
(S-1)
Contents of
(PS) Processor Status
Register Restored on Stack
(S-1) I Flag set high
Jump Vector Fetched
Interrupt Routine
Execute RTS
(S)
(S+1)
Return Address
Restored
(PCl)
(S)
M(S)
(S+1)
(PCh)
M(S)
(PC)
(PC+1)
Execute RTI
Contents of
(S)
(S+1) Processor Status
Register Restored
(PS)
M(S)
(S)
(S+1)
(PCl)
(S)
M(S)
(S+1)
Return Address
Restored
(PCh)
M(S)
Figure 2-2. Register Push and Pop when Servicing Interrupts and Calling Subroutines
Note 1. The condition to enable an interrupt: Interrupt enable bit is set to a “1” and Interrupt inhibit
flag (I flag) is a “0”.
Note 2. When an interrupt occurs, the address of the next instruction to be executed is stored on the
stack. When a subroutine is called, the address of (next instruction -1) to be executed is stored
on the stack.
2.1.6 Processor Status Register
The processor status (PS) register is an 8-bit register consisting of flags that indicate the status of the
processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C),
Zero (Z), Overflow (V), or the Negative (N) flags.
After reset, the I flag is set to a “1”, but all other flags are undefined. Because the T and D flags
directly affect arithmetic operations, they should be initialized in the beginning of a program.
Carry Flag (C)
The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately
after an arithmetic operation. It is also affected by shift and rotate instructions. The C flag can be
set directly by the set carry (SEC) instruction and cleared by the clear carry (CLC) instruction.
Central Processing Unit
7/9/98
2-5
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