M37640E8 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Table 1-2. Pin Description
Name I/O
Description
Pin #
P73/IBF1/
HLDA
I/O
CMOS I/O port or IBF1 output to master CPU for data
mutually exclusive. IBF1 has priority over HLDA.
bus
buffer
1,
or
HLDA
pin.
IBF1
and
HLDA
are
66
P74/OBF1 I/O CMOS I/O port or OBF1 output to master CPU for data bus buffer 1.
65
P80/UTXD2/
SRDY
I/O
CMOS
priority
I/O port or
over SIO.
UART2
pin
UTXD2
or
SIO
pin
SRDY.
UART2
and
SIO
are
mutually
exclusive,
UART2
has
32
P81/URXD2/
SCLK
I/O
CMOS I/O
has priority
port or UART2
over SIO.
pin
URXD2
or
SIO
pin
SCLK.
UART2
and
SIO
are
mutually
exclusive,
UART2
31
P82/CTS2/
SRXD
I/O
CMOS
priority
I/O port or
over SIO.
UART2
pin
CTS2
or
SIO
pin
SRXD.
UART2
and
SIO
are
mutually
exclusive,
UART2
has
30
P83/RTS2/
STXD
I/O
CMOS
priority
I/O port or
over SIO.
UART2
pin
RTS2
or
SIO
pin
STXD.
UART2
and
SIO
are
mutually
exclusive,
UART2
has
29
P84/UTXD1 I/O CMOS I/O port or UART1 pin UTXD1.
P85/URXD1 I/O CMOS I/O port or UART1 pin URXD1.
P86/CTS1 I/O CMOS I/O port or UART1 pin CTS1.
P87/RTS1 I/O CMOS I/O port or UART1 pin RTS1.
AVcc,AVss I Power supply inputs for analog circuitry AVcc = 4.15~ 5.25V, AVss = 0V
CNVss
I
Controls the processor mode of the chip. Normally connected to Vss or Vcc. When the MCU is in EPROM
program mode, this pin supplies the programming voltage to the EPROM.
28
27
26
25
17,19
9
Vcc,Vss
I Power supply inputs: Vcc = 4.15~ 5.25V, Vss = 0V
16/74,
13/73
RESET
I
To enter the reset state, this pin must be kept L for more that 2µs (20 Φ cycles under normal Vcc conditions). If
the crystal or ceramic resonator requires more time to stabilize, extend this L level time appropriately.
10
XCin
XCout
Xin
Xout
LPF
I An external ceramic or quartz crystal oscillator can be connected between the XCin and XCout pins. If an
12
O external clock source is used, connect the clock source to the XCin pin and leave the XCout pin open.
11
I
O
Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz
crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock
source to the Xin pin and leave the Xout pin open.
14
15
O Loop filter for the frequency synthesizer.
18
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2µf or larger
Ext. Cap
I capacitor should connect between this pin and Vss to ensure proper operation of the USB line driver. The
72
voltage converter is enabled by setting bit 4 of the USB control register (001316) to a “1”.
D+/D- Line driver notes: In order to match the USB cable impedance, a series resistor of 33Ω, 1%,
1/8 W should be connected to each USB line; i.e. on D+ (pin 70) and on D- (pin 71). Also, a
coupling capacitor with the recommended value of 33pF should be connected between D+ and D- after
the 33Ω series resistors. If the USB line is improperly terminated or not matched, signal fidelity will
suffer, resulting in excessive overshoot or undershoot. This will potentially introduce bit errors.
VDD/VSS notes: In order to reduce the effects of the inductance of the traces on the board,
decoupling capacitors should be connected between pins 73(VSS) and 74(VDD), 13(VSS) and 16(VDD),
and 17(AVDD) and 19(AVSS). Recommended values are a 4.7 µF in parallel with a 0.1 µF.
Pin 73
(VSS)
C1 C2
Pin 74
(VDD)
Pin 13
(VSS)
C1 C2
Pin 16
(VDD)
Pin 17
(AVSS)
C1 C2
Pin 19
(AVDD)
C1 = 4.7 µF
C2 = 0.1 µF
Figure 1-3. VDD/VSS decoupling capacitor connections
1-8
6/2/98
Pin Description and Layout
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