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M37640E8

Single-Chip 8-BIT CMOS Microcontroller M37640E8-XXXFP Specification

MITSUBISHI ELECTRIC  

7600 Series

M37640E8-XXXF Preliminary Specification

Mitsubishi Microcomputers

Zero Flag (Z)

The Z flag is set if the result of an arithmetic operation or a data transfer is “0”, and cleared if the

result is anything other than “0”.

Interrupt Disable Flag (I)

The I flag disables all interrupts except for the interrupt generated by the BRK instruction and any

non-maskable interrupts, if available. Interrupts are disabled when the I flag is “1”. When an

interrupt occurs, this flag is automatically set to a “1” to prevent other interrupts from interfering

until the current interrupt service routine is completed. The I flag can be set by the set interrupt

disable (SEI) instruction and cleared by the clear interrupt disable (CLI) instruction.

Decimal Mode Flag (D)

The D flag determines whether additions and subtractions are executed in binary or decimal. Binary

arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal

correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for

decimal arithmetic. The D flag can be set by the set decimal mode (SED) instruction and cleared by

the clear decimal mode (CLD) instruction.

Break Flag (B)

The B flag is used to indicate whether the current interrupt was generated by the BRK instruction.

The BRK flag in the processor status register is nominally “0”. When the BRK instruction is used

to generate an interrupt, the processor status register is pushed onto the stack with the break flag set

to a “1”. The saved processor status is the only place where the break flag is ever set.

Index X Mode Flag (T)

When the T flag is “0”, arithmetic operations are performed between accumulator and memory, and

the results are stored in the accumulator. When the T flag is “1”, direct arithmetic operations and

direct data transfers are enabled between memory and memory, as well as between I/O and I/O. The

result of an arithmetic operation performed on data in memory location 1 and memory location 2 is

stored in memory location 1.

The address of memory location 1 is specified by index register X, and the address of memory

location 2 is specified by normal addressing modes. The T flag can be set by the set T flag (SET)

instruction and cleared by the clear T flag (CLT) instruction. Because the T flag directly affects

calculations, it should be initialized after a reset.

Overflow Flag (V)

The V flag is used during the addition or subtraction of one byte of signed data. It is set if the

result exceeds the range from +127 to -128. When the BIT instruction is executed, bit 6 of the

memory location operated on by the BIT instruction is stored in the overflow flag. The V flag can

be cleared by the CLV instruction, but there is no set instruction. In decimal mode, the V flag is

invalid.

Negative Flag (N)

The N flag is set if the result of an arithmetic operation or data transfer is negative, that is (bit 7

is “1”). When the BIT instruction is executed, bit 7 of the memory location operated by the BIT

instruction is stored in the negative flag. There are no instructions for directly setting or clearing the

N flag.

2-6

7/9/98

Central Processing Unit

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