M37640E8 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
Reset
Stop Note 1
Wait
Stop Note 1
Wait
Stop Note 1
Wait
Stop Note 1
Wait
Xin clock on
FSC0
Xin clock on
CPMA6
Xin clock on
XCin clock stopped
1
XCin clock stopped
1
XCin clock stopped
PLL clock stopped
Φ=f(Xin)/4 Note 2
0
PLL clock on Note 3
Φ=f(Xin)/4 Note 2
0
PLL clock on
Φ=f(PLL)/2
Wait
CPMA=0C, FSC=60
CPMA=0C, FSC=41
CPMA=4C, FSC=41
10
CPMA4
Xin clock on
FSC0
Xin clock on
CPMA6 Xin clock on
XCin clock on
1
XCin clock on
1
XCin clock on
PLL clock stopped
Φ=f(Xin)/4 Note 2
0
PLL clock on Note 3
Φ=f(Xin)/4 Note 2
0
PLL clock on
Φ=f(PLL)/2
Wait
CPMA=1C, FSC=60
CPMA=1C, FSC=41
CPMA=5C, FSC=41
10
CPMA7
Xin clock on
XCin clock on
FSC0
1
Xin clock on
XCin clock on
CPMA6
1
Xin clock on
XCin clock on
PLL clock stopped
Φ=f(XCin)/2
0
PLL clock on Note 3
Φ=f(XCin)/2
0
PLL clock on
Φ=f(PLL)/2
Wait
CPMA=9C, FSC=60
CPMA=9C, FSC=41
CPMA=DC, FSC=41
10
CPMA5 Note 4
Xin clock stopped
FSC0
Xin clock stopped
CPMA6 Xin clock stopped
XCin clock on
1
XCin clock on
1
XCin clock on
PLL clock stopped
Φ=f(XCin)/2
0
PLL clock on Note 3
Φ=f(XCin)/2
0
PLL clock on
Φ=f(PLL)/2
Wait
CPMA=BC, FSC=68
CPMA7=BC, FSC=49
CPMA7=FC, FSC=49
Note 1: Stop mode stops the oscillators which are also the inputs to the frequency synthesizer.
However, the frequency synthesizer is not disabled and so its output is unstable. So, always
set the system clock to an external oscillator and disable the frequency synthesizer before
entering stop mode.
Note 2: Φ=f(Xin)/4 can be inter-changed with Φ=f(Xin)/2 by setting CCR7 to “1”. The same
flow-chart applies for both cases.
Note 3: The input to the frequency synthesizer is independent of the system clock. It can be
either Xin or XCin depending on bit 3 of FSC. In the above flow, the input has been chosen
to be the same as the system clock only for simplicity. The oscillator selected to be the input
to the frequency synthesizer must be enabled before the frequency synthesizer is enabled.
Note 4: The input clock for the frequency synthesizer must be set to XCin by setting FIN
(bit 3 of FSC) to a “1” before Xin oscillation can be disabled.
Note: CPMA values shown assume single-chip mode with stack in one page.
Figure 2-6. Clock Flow Diagram
Oscillator Circuit
7/9/98
2-9
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