HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS

The V292BMC Revision D Burst DRAM Controller is an enhanced version of the previous V292BMC with improved timing and provides dedicated Power and Ground rails to support the increasingly popular 3.3V DRAM modules. Timing parameters are also improved over the older versions of the device.

• Pin/Software compatible with earlier V292BMC.
• Direct interfaces to Am29030/40 processors.
• 3.3V DRAM interface support.
• Near SRAM performance achieved with DRAM.
• Supports up to 512Mb of DRAM.
• Interleaved or non-interleaved operation.
• Supports symmetric and non-symmetric arrays.
• Software-configured operational parameters.
• Integrated Page Cache Management.
• 2Kbyte burst transaction support.
• On chip memory address multiplexer/drivers.
• Two 24-bit timers, 8-bit bus watch timer.
• Up to 40MHz operation.
• Low cost 132-pin PQFP package.