V292BMC-33LPN 데이터 시트보기 (PDF) - QuickLogic Corporation

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V292BMC-33LPN

HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS

QuickLogic Corporation 

V292BMC Rev.D

Signal

A[31:2]

ALE

I/D

BWE[3:0]

R/W

REQ

RDY

Table 3: Signal Descriptions (cont’d)

Type R

Description

I

Local address bus.

Address Latch Enable: controls a set of transparent latches on the

address bus. When asserted high, the address input flows through

I

the latch. When ALE is low, the internal address holds the previous

value. With an Am29030/40 processor ALE is not typically used and

has an internal pull-up resistor that will keep it high when not con-

nected (to provide backward pin compatibility with earlier versions).

I

Data/Code.

I

Local bus byte write enables.

I

Read/write.

I

Asserted low to indicate the beginning of a bus cycle.

O12 Z Local bus data ready.

PRDY

I

Processor ready

SUP/US

I

BURST

I

Indicates supervisor mode. Required for access to configuration reg-

isters.

Burst request.

ERR

INT

O12 H Bus Time-out error.

Local interrupt request. This signal is asserted when the 24-bit

O12 H counter reaches terminal count, and interrupt out is enabled. May

be programmed for pulse or level operation.

RESET

I

Local bus reset signal.

MEMCLK

I

Local bus clock.

ID[2:0]

I

These inputs select the address offset of the configuration registers.

Power and Ground Signals

Signal

Type R

Description

Vcc

-

POWER leads intended for external connection to a 5V Vcc plane

Vcc3

-

POWER for DRAM control outputs. Can be connected to 3.3V or 5V.

GND

-

GROUND leads intended for external connection to a GND plane.

a. R indicates state during reset.

4

V292BMC Rev D Data Sheet Rev 3.2

Copyright © 1998, V3 Semiconductor Inc.

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